908E621_12 Datasheet, PDF (26/60 Pages) Freescale Semiconductor, Inc – Integrated Quad Half bridge and Triple High Side Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 6. Operating Modes Overview
Device Mode Voltage Regulator Wake-up Capabilities
Reset
V_DD ON
N/A
Normal Request
V_DD ON
N/A
RST_A
Output
MCU monitoring/
Watchdog Function
Power Stages
LOW
Disabled
Disabled
HIGH
t_NORMREQ (80 ms
typical) timeout to set
PSON bit in System
Control Register
Disabled
LIN Interface
Disabled
Disabled
Normal (Run)
V_DD ON
N/A
HIGH
Window Watchdog
active if enabled
Enabled
Enabled
Stop
V_DD ON with limited
current capability
LIN wake-up,
L0 state change
(SPI PSON=1)⁽³⁵⁾
HIGH
Disabled
Disabled
Recessive state with
wake-up capability
Sleep
V_DD OFF
LIN wake-up
L0 state change
LOW
Disabled
Disabled
Recessive state with
wake-up capability
Notes
35. The SPI is still active in Stop mode. However, due to the limited current capability of the voltage regulator in Stop mode, the PSON bit
has to be set before the increased current caused from a running MCU causes an LVR.
OPERATING MODES OF THE MCU
For a detailed description of the operating modes of the
MCU, refer to the MC68HC908EY16 datasheet.
INTERRUPTS
The 908E621 has seven different interrupt sources. An
interrupt pulse on the IRQ_A pin is generated to report an
event or fault to the MCU. All interrupts are maskable and can
be enabled/disabled via the SPI (Interrupt Mask Register).
After reset, all interrupts are automatically disabled.
Low Voltage Interrupt
Low voltage interrupt (LVI) is related to external supply
voltage VSUP. If this voltage falls below the LVI threshold, it
will set the LVIF bit in the Interrupt Flag Register. If the low
voltage interrupt is enabled (LVIE = 1), an interrupt will be
initiated.
During Sleep and Stop mode, the low voltage interrupt
circuitry is disabled.
High Voltage Interrupt
The High voltage Interrupt (HVI) is related to the external
supply voltage VSUP. If this voltage rises above the HVI
threshold, it will set the HVIF bit in the Interrupt Flag Register.
If the High voltage Interrupt is enabled (HVIE = 1), an
interrupt will be initiated.
During Stop and Sleep mode, the HVI circuitry is disabled.
High Temperature Interrupt
The high temperature interrupt (HTI) is generated by the
on chip temperature sensors. If the chip temperature is above
the HTI threshold, the HTIF bit in the Interrupt Flag Register
will be set. If the high temperature interrupt is enabled (HTIE
= 1), an interrupt will be initiated.
During Stop and Sleep mode, the HTI circuitry is disabled.
LIN Interrupt
The LIN Interrupt is related to the Stop mode. If the LIN
interrupt is enabled (LINIE = 1) in Stop mode, an interrupt is
asserted if a rising edge is detected, and the bus was
dominant longer than T_PROPWL. After the wake-up / interrupt,
the LINIF indicates the reason for the wake-up / interrupt.
Power Stage Fail Interrupt
The power stage fail flag indicates an error condition on
any of the power stages (see Figure 14, page 27). If the
power stage fail interrupt is enabled (PSFIE = 1), an interrupt
will be initiated if:
During Stop and Sleep mode, the PSFI circuitry is
disabled.
HO Input Interrupt
The H0 interrupt flag H0IF is set in run mode by a state
change of the H0F flag (rising or falling edge on the enabled
input). The interrupt function is available if the input is
selected as General Purpose, or as a 2-pin Hall sensor input.
The interrupt is maskable with the H0IE bit in the Interrupt
Mask Register.
During Stop and Sleep mode, the H0I circuitry is disabled.
908E621
26
Analog Integrated Circuit Device Data
Freescale Semiconductor