908E621_12 Datasheet, PDF (44/60 Pages) Freescale Semiconductor, Inc – Integrated Quad Half bridge and Triple High Side Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SS
MOSI
MISO
Read/Write, Address, Parity
R/W A4 A3 A2 A1 A0
P
X
System Status Register
S7 S6 S5 S4 S3 S2 S1 S0
Data (Register write)
D7 D6 D5 D4 D3 D2 D1 D0
Data (Register read)
D7 D6 D5 D4 D3 D2 D1 D0
SPSCK
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Figure 29. SPI Protocol
Slave latch
data
• During the inactive phase of SS, the new data transfer
will be prepared. The falling edge on the SS line,
indicates the start of a new data transfer (framing), and
puts MISO in the low impedance mode. The first valid
data are moved to MISO with the rising edge of SPSCK.
• The MOSI, MISO will change data on a rising edge of
SPSCK.
• The MOSI, MISO will be sampled on a falling edge of
SPSCK.
• The data transfer is only valid, if exactly 16 sample clock
edges are present in the active phase of SS.
• After a write operation, the transmitted data will be
latched into the register by the rising edge of SS.
• Register read data is internally latched into the SPI at
the time when the parity bit is transferred
• SS high will force MISO to high-impedance
Master Address Byte
A4 - A0
Includes the address of the desired register.
R/W
Includes the information, if it is a read or a write operation.
• If R/W = 1 (read operation), the second byte of master
contains no valid information, and the slave just
transmits back register data.
• If R/W = 0 (write operation), the master sends data to be
written in the second byte, the slave sends concurrently
contents of selected register prior to write operation,
and the write data is latched in the SMARTMOS
registers on rising edge of SS.
Parity P
Completes the total number of 1 bits of (R/W,A[4-0]) to an
even number. e.g. (R/W,A[4-0]) = 100001 -> P0 = 0.
The parity bit is only evaluated during a write operations
and ignored for read operations.
Bit X
Not used
Master Data Byte
This byte includes data to be written, or no valid data,
during a read operation.
Slave Status Byte
This byte always includes the contents of the system
status register ($0C), independent if it is a write or read
operation, or which register was selected.
Slave Data Byte
This byte includes the contents of selected register, during
a write operation, it includes the register content prior to the
write operation.
SPI REGISTER OVERVIEW
Table 12 summarizes the SPI Register addresses and the
bit names of each register.
908E621
44
Analog Integrated Circuit Device Data
Freescale Semiconductor