908E621_12 Datasheet, PDF (45/60 Pages) Freescale Semiconductor, Inc – Integrated Quad Half bridge and Triple High Side Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 12. SPI Register Overview
Addr
Register Name
R/W
7
6
5
System Control
R
0
0
$00
(SYSCTL)
PSON
W
STOP
SLEEP
Half-bridge Output
R
$01
(HBOUT)
HB4_H
W
HB4_L HB3_H
High Side Output
R
$02
(HSOUT)
HVDDON
W
0
HS3PWM
Half-bridge Status and ^R
0
0
$03
Control (HBSCTL)
W
CRM
High Side Status and ^R
0
0
$04
Control (HSSCTL)
HVDDOCF
W
R
$05
Reserved
W
R
$06
Reserved
W
H0/L0 Status and
R
L0F
0
0
$07
Control (HLSCTL)
W
A0 and Multiplexer
R
$08 _{Control (A0MUCTL)}
W
CSON CSSEL1 CSSEL0
Interrupt Mask
R
$09
(IMR)
L0IE
W
H0IE
LINIE
Interrupt Flag
R
$0A
(IFR)
L0IF
W
H0IF
LINIF
Watchdog Control
R
$0B
(WDCTL)
WDRE
W
WDP1
WDP0
System Status
R
LINCL
HTIF
VF
$0C
(SYSSTAT)
W
Reset Status
R
$0D
(RSR)
POR
W
PINR
WDR
System Test
R
$0E
(SYSTEST)
W
System Trim 1
R
$0F
(SYSTRIM1)
HVDDT1 HVDDT0 reserved
W
System Trim 2
R
0
0
0
$10
(SYSTRIM2)
W _{CRHBHC1 CRHBHC0 CRHB5}
$11
System Trim 3
(SYSTRIM3)
R
0
0
0
W _{CRHBHC3 CRHBHC2 CRHS5}
Bit
4
3
HTIS1
HTIS0
HB3_L
HB2_H
HS2PWM HS1PWM
0
HB4OCF
0
0
reserved
reserved
H0F
H0OCF
CSA
SS3
HTRD
HTIE
0
HTIF
0
0
H0F
HVDDF
HTR
LVR
reserved
reserved
itrim3
0
CRHB4
0
CRHS4
0
CRHB3
0
CRHS3
2
VIS
HB2_L
HS3ON
HB3OCF
HS3OCF
H0EN
SS2
LVIE
LVIF
0
HSF
0
itrim2
0
CRHB2
0
CRHS2
1
SRS1
HB1_H
HS2ON
HB2OCF
HS2OCF
H0PD
SS1
HVIE
HVIF
0
HBF
LINWF
itrim1
0
CRHB1
0
CRHS1
0
SRS0
HB1_L
HS1ON
HB1OCF
HS1OCF
H0MS
SS0
PSFIE
PSFIF
0
WDRST
0
L0WF
itrim0
0
CRHB0
0
CRHS0
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E621
45