908E621_12 Datasheet, PDF (29/60 Pages) Freescale Semiconductor, Inc – Integrated Quad Half bridge and Triple High Side Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RESET SOURCE
High Temperature Reset
The device is protected against high temperature. When
the chip temperature exceeds a certain temperature, a reset
(HTR) is generated. The reset is flagged by the HTR bit in the
Interrupt Flag Register. A HTR event will reset all registers in
the SPI excluding the RSR.
The HTR can be disabled by bit HTRD in the Interrupt
Mask register.
Note: Disabling the high temperature reset can lead to
destruction of the part in cases of high temperature. This bit
was foreseen for test purposes only!
Watchdog Reset
The watchdog module generates a reset, because of a
watchdog timeout or wrong watchdog timer reset. Reset is
flagged by the WDR bit in the Reset Status Register. A
watchdog reset event will reset all registers in the SPI
excluding the RSR.
Main VREG Low Voltage Reset
The LVR is related to the Main VDD. If the voltage falls
below a certain threshold, it will pull down the RST_A pin.
Reset is flagged by the LVR bit in the Reset Status Register.
An LVR event will reset all register in the SPI excluding the
RSR.
Power On Reset
The POR is related to the internal 5.0 V supply. If the
device detects a power on, the POR bit in the Reset Status
Register (RSR) is set. A power on reset will reset all register
in the SPI including the RSR and set the POR bit.
The Power On Reset circuitry will force the RST_A pin low
for t_RST after the V_DD has reached its nominal value (above
LVR Threshold). Also see Figure 10, page 18).
Reset Pin / External Reset
An external reset can be applied by pulling down the
RST_A pin. The reset event is flagged by the PINR bit in the
reset status register.
Reset Status Register
This register contains five flags that shows the source of
the last reset. A power-on-reset sets the POR bit and clears
all other bits in the Reset Status Register. All bits can be
cleared by writing a one to the corresponding bit. Uncleared
bits remain set as long as they are not cleared by a power-
on-reset or by software.
In addition, the register includes two flags which will
indicate the source of a wake-up from Sleep mode: Either LIN
bus activity, or an event on the L0 wake-up input pin.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Register Name and Address: RSR - $0D
Bit7 6
5
4
3
2
1 Bit0
Read
POR PINR WDR HTR LVR
Write
0
LINWF LOWF
POR 1
0
0
0
0
0
0
0
POR— Power On Reset bit
This read/write bit is set after power on. Bit is cleared by
writing a logic “1” to this location.
1 = Reset due to power on
0 = no power on reset
PINR— Reset Forced from External Reset Pin Bit
This read/write bit is set after a reset was forced on the
external reset RST_A pin. The bit is cleared by writing an
logic “1” to this location.
1 = reset source is external reset pin
0 = no external reset
WDR— Watch Dog Reset Bit
This read/write flag is set due to a watchdog timeout or
wrong watchdog timer reset. Clear WDR by writing a logic “1”
to WDR.
1 = reset source is watchdog
0 = no watchdog reset
HTR— High Temperature Reset Bit
This read/write bit is set if the chip temperature exceeds a
certain value. The bit is cleared by writing a logic “1” to this
location.
1 = reset due to high temperature condition
0 = no high temperature reset
LVR— Low Voltage Reset Bit
This read/write bit is set if the external V_DD voltage coming
from the main voltage regulator falls below a certain value.
The bit is cleared by writing a logic “1” to this location.
1 = reset due to low voltage condition
0 = no low voltage reset
LINWF— LIN Wake-up Flag
This read/write bit is set if a bus activity was the case of an
wake-up. The bit is cleared by writing a logic “1” to this
location.
1 = Wake-up due to bus activity
0 = no wake-up due to bus activity
L0WF— L0 Wake-up Flag
This read/write bit is set if a event on the L0 pin caused an
wake-up. The bit is cleared by writing a logic “1” to this
location.
908E621
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