MC68HC11EA9 Datasheet, PDF (51/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
SCCR1 — SCI Control Register 1
BIT 7
6
5
LOOPS WOMS
—
RESET:
0
0
0
4
3
2
M
WAKE
ILT
0
0
0
$102A
1
BIT 0
PE
PT
0
0
LOOPS — SCI LOOP Mode Enable
0 = SCI transmit and receive operate normally
1 = SCI transmit and receive are disconnected from TxD and RxD pins, and transmitter output is
fed back into the receiver input
WOMS — Wired-Or Mode Option for PD[1:0] (See also DWOM bit in SPCR.)
0 = TxD and RxD operate normally
1 = TxD and RxD are open drains if operating as an output
Bit 5 — Not implemented
Always reads zero
M — Mode (Select Character Format)
0 = Start, 8 data bits, 1 stop bit
1 = Start, 9 data bits, 1 stop bit
WAKE — Wake-Up by Address Mark/Idle
0 = Wake-up by IDLE line recognition
1 = Wake-up by address mark (most significant data bit set)
ILT — Idle Line Type
0 = Short (SCI counts consecutive ones after start bit)
1 = Long (SCI counts ones only after stop bit)
PE — Parity Enable
0 = Parity disabled
1 = Parity enabled
PT — Parity Type
0 = Parity even (even number of ones causes parity bit to be zero, odd number of ones causes par-
ity bit to be one)
1 = Parity odd (odd number of ones causes parity bit to be zero, even number of ones causes parity
bit to be one)
SCCR2 — SCI Control Register 2
$102B
BIT 7
6
5
4
3
TIE
TCIE
RIE
ILIE
TE
RESET:
0
0
0
0
0
2
1
BIT 0
RE
RWU
SBK
0
0
0
TIE — Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
TCIE — Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
RIE — Receiver Interrupt Enable
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag is set
MC68HC11EA9
MC68HC11EA9TS/D
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