MC68HC11EA9 Datasheet, PDF (44/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
PLLTO ÷ 64 CLOCK *
(FROM MAIN TIMER)
PAOVI
PAOVF
PAII
PAIF
1
INTERRUPT
REQUESTS
2
MCU PIN
PA7/
PAI/
OC1
TMSK2 INT ENABLES
INPUT BUFFER
AND
EDGE DETECTOR
OUTPUT
BUFFER
2:1
MUX
DATA
BUS
TFLG2 INTERRUPT STATUS
PAI EDGE
PAEN
DISABLE
FLAG SETTING
CLOCK
OVERFLOW
PACNT 8-BIT COUNTER
ENABLE
PAEN
FROM
MAIN TIMER OC1
FROM DATA DIRECTION
BIT FOR PORT A PIN 7
PACTL CONTROL
* REFER TO TIMER AND PLL BLOCK DIAGRAMS.
INTERNAL
DATA BUS
EA9 PLS ACC BLOCK
Figure 10 Pulse Accumulator Block Diagram
PACTL — Pulse Accumulator Control
$1026
BIT 7
6
5
4
3
—
PAEN PAMOD PEDGE
—
RESET:
0
0
0
0
0
2
I4/O5
0
1
RTR1
0
BIT 0
RTR0
0
Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset in
normal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time.
Bit 7 — Not Implemented
Always reads zero
PAEN — Pulse Accumulator Enable
0 = Periodic interrupts are disabled
1 = Interrupts are generated at the rate determined by RTR[1:0]
PAMOD — Pulse Accumulator Mode Select
0 = PCNT overflow interrupts are disabled
1 = Interrupts are generated each time PCNT rolls over to $0000
MC68HC11EA9
44
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MC68HC11EA9TS/D
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