MC68HC11EA9 Datasheet, PDF (37/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
TOC1–TOC4 — Timer Output Compare
$1016 BIT 15
14
13
12
11
10
$1017
BIT 7
6
5
4
3
2
$1016–$101D
9
BIT 8 TOC1 (HI)
1
BIT 0 TOC1 (LO)
$1018 BIT 15
14
13
12
11
10
$1019
BIT 7
6
5
4
3
2
9
BIT 8 TOC2 (HI)
1
BIT 0 TOC2 (LO)
$101A BIT 15
14
13
12
11
10
$101B
BIT 7
6
5
4
3
2
9
BIT 8 TOC3 (HI)
1
BIT 0 TOC3 (LO)
$101C BIT 15
14
13
12
11
10
$101D
BIT 7
6
5
4
3
2
All TOCx register pairs reset to $FFFF.
9
BIT 8 TOC4 (HI)
1
BIT 0 TOC4 (LO)
TI4/O5 — Timer Input Capture 4/Output Compare 5
$101E–$101F
BIT 15
14
13
12
11
10
BIT 7
6
5
4
3
2
9
BIT 8 TCNT (HI)
1
BIT 0 TCNT (LO)
This is a shared register and is either input capture 4 or output compare 5 depending on the state of bit
I4/O5 in PACTL. Writes to TI4/O5 have no effect when this register is configured as input capture 4. The
TI4/O5 register pair resets to $FFFF.
TCTL1 — Timer Control 1
$1020
BIT 7
6
5
4
3
2
1
BIT 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
RESET:
0
0
0
0
0
0
0
0
Table 14 Output Compare Channel Configuration
OMx OLx
Action on Successful Compare
0
0
None — Output Compare Channel (OCx) disabled
0
1
Toggle OCx output pin logic level
1
0
Drive OCx output pin low
1
1
Drive OCx output pin high
TCTL2 — Timer Control 2
RESET:
BIT 7
EDG4B
0
6
EDG4A
0
5
EDG1B
0
4
EDG1A
0
3
EDG2B
0
2
EDG2A
0
1
EDG3B
0
BIT 0
EDG3A
0
Table 15 Input Capture Channel Configuration
EDGxB EDGxA
0
0
0
1
1
0
1
1
Input Capture Configuration
Input Capture Channel (ICx) disabled
Capture on rising edge on ICx input pin
Capture on falling edge on ICx input pin
Capture on any edge on ICx input pin
$1021
MC68HC11EA9
MC68HC11EA9TS/D
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