MC68HC11EA9 Datasheet, PDF (17/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
5. Clear the PGM bit to turn off the V_PPE voltage.
6. Clear all bits in the PPROG register to reconfigure the EPROM address and data buses for nor-
mal operation.
NOTE
PROG mode is initiated when RESET, MODA, and MODB pins are pulled low (the
pin state required to enter bootstrap mode). This means that if these three pins are
pulled low and V_PPE is present on the XIRQ pin, the EPROM will be programmed.
To prevent this, place a pull-up resistor on the IRQ pin (CE pin in PROG mode).
When the device goes into reset, the PGM bit is forced to the voltage disable state
(EPGM = 0) before the address/data latches are enabled to the external input lines.
Only after this occurs is voltage control returned to the IRQ pin.
4.9.3 Programming EPROM with Downloaded Data
When using this method, the EPROM is programmed by software while in the special test or bootstrap
modes. User-developed software can be uploaded through the SCI, or a ROM resident EPROM pro-
gramming utility can be used. To use the resident utility, bootload a three-byte program consisting of a
single jump instruction to $BF00. $BF00 is the starting address of a resident EPROM programming util-
ity. The utility program sets the X and Y index registers to default values, then receives programming
data from an external host and puts it in EPROM. The value in IX determines programming delay time.
The value in IY is a pointer to the first address in EPROM to be programmed (default = $D000).
When the utility program is ready to receive programming data, it sends the host the $FF character.
Then it waits. When the host sees the $FF character, the EPROM programming data is sent, starting
with the first location in the EPROM array. After the last byte to be programmed is sent and the corre-
sponding verification data is returned, the programming operation is terminated by resetting the MCU.
PPROG — EPROM and EEPROM Programming Control Register
RESET:
BIT 7
ODD
0
6
EVEN
0
5
ELAT*
0
4
BYTE
0
3
ROW
0
2
ERASE
0
* MC68HC711EA9 only.
1
EELAT
0
BIT 0
PGM
1
$103B
ODD — Program Odd Rows in Half of EEPROM (TEST)
Refer to 4.10 EEPROM.
EVEN — Program Even Rows in Half of EEPROM (TEST)
Refer to 4.10 EEPROM.
ELAT — EPROM/OTPROM Latch Control
When ELAT = 1, writes to EPROM cause address and data to be latched and the EPROM/OTPROM
cannot be read. ELAT can be read any time. ELAT can be written any time except when EPGM = 1;
then the write to ELAT is disabled. For MC68HC711EA9, EPGM enables the high voltage necessary
for both EPROM/OTPROM and EEPROM programming. For MC68HC711EA9 ELAT and EELAT are
mutually exclusive and cannot both equal one.
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming
BYTE — Byte/Other EEPROM Erase Mode
Refer to 4.10 EEPROM.
ROW — Row/All EEPROM Erase Mode
Refer to 4.10 EEPROM.
MC68HC11EA9
MC68HC11EA9TS/D
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