MC68HC11EA9 Datasheet, PDF (22/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

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5 Resets and Interrupts
All M68HC11 MCUs have three reset vectors and 18 interrupt vectors. The reset vectors are as follows:
• RESET, or Power-On Reset
• Clock Monitor Fail
• COP Failure
The 18 interrupt vectors service 22 interrupt sources (3 non-maskable, 19 maskable). The 3 non-
maskable interrupt sources are as follows:
• Illegal Opcode Trap
• Software Interrupt
• XIRQ Pin (X Interrupt)
On-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter-
rupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized accord-
ing to a default arrangement; however, any one source can be elevated to the highest maskable priority
position by a software-accessible control register (HPRIO). The HPRIO register can be written at any
time, provided bit I in the CCR is set.
Eighteen interrupt sources in the MC68HC(7)11EA9 MCUs are subject to masking by the global inter-
rupt mask bit (bit I in the CCR). In addition to the global bit I, all of these sources, except the external
interrupt (IRQ) pin, are controlled by local enable bits in control registers. Most interrupt sources in the
M68HC11 have separate interrupt vectors; therefore, there is usually no need for software to poll control
registers to determine the cause of an interrupt.
For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the
normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system
is cleared by the automatic clearing mechanism invoked by a read of the SCI status register while RDRF
is set, followed by a read of the SCI data register. The normal response to an RDRF interrupt request
would be to read the SCI status register to check for receive errors, then to read the received data from
the SCI data register. These two steps satisfy the automatic clearing mechanism without requiring any
special instructions.
The computer operating properly (COP) watchdog and the clock monitor are both circuits that force a
reset sequence when a malfunctioning clock is encountered. The COP function forces a reset when a
timeout occurs. The timeout period is determined by programming CR[1:0] in OPTION register. The
clock monitor circuit forces a reset sequence whenever the clock is slow or absent. The CME bit in the
OPTION register enables the clock monitor circuit. To use STOP mode the clock monitor must be dis-
abled before the STOP instruction is executed or a reset sequence will occur.
Refer to the following table for a list of interrupt and reset vector assignments.
Table 7 Interrupt and Reset Vector Assignments
Vector Address
Interrupt Source
CCR Mask Local Mask Priority
(1 = High)
FFC0, C1 — FFD4, D5 Reserved
—
FFD6, D7
SCI Serial System
Bit I
• SCI Receive Data Register Full
• SCI Receiver Overrun
• SCI Transmit Data Register Empty
• SCI Transmit Complete
• SCI Idle Line Detect
FFD8, D9
Reserved
—
—
—
18
RIE
RIE
TIE
TCIE
ILIE
—
—
MC68HC11EA9
22
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