MC68HC11EA9 Datasheet, PDF (28/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
Table 11 Strobed and Handshake Parallel I/O Control Bit Summary
STAF
Clearing
Sequence HNDS OIN PLS
EGA
Port B
Simple Read PIOC 0 X
strobed with STAF = 1
X
0
mode
then read
PORTCL
1
Inputs latched
into PORTCL
on any
active edge
on STRA
Port C
STRB pulses
on writes to
PORTB
Full
Read PIOC 1
input with STAF = 1
handshake then read
mode
PORTCL
Full
Read PIOC 1
output with STAF = 1
handshake then write
mode
PORTCL
0
0 = STRB
active level
1
1 = STRB
active pulse ⁰
Inputs latched
into PORTCL
on any
active edge
on STRA
Normal output
port, unaffected
in handshake
modes
1 _{0 = STRB 0}
active level
1 = STRB ¹
active pulse
Follow
DDRC
Port C
Driven
STRA
Active Edge
Driven as outputs if Normal output
STRA at active port, unaffected
level; follows
in handshake
DDRC if STRA not
modes
at active level
Follow
DDRC
Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at
reset. Port pins are either driven to a specified logic level or are configured as high impedance inputs.
I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the
corresponding latches are dependent upon the electrical state of the pins during reset. In port descrip-
tions, an "I" indicates this condition. Port pins that are driven to a known logic level during reset are
shown with a value of either one or zero. Some control bits are unaffected by reset. Reset states for
these bits are indicated with a "U".
PORTA — Port A Data
$1000
RESET:
Alt. Pin
Func.:
And/or
BIT 7
PA7
I
PAI
OC1
6
PA6
I
OC2
OC1
5
PA5
I
OC3
OC1
4
3
2
PA4
PA3
PA2
I
I
I
OC4 IC4/OC5 IC1
OC1
OC1
—
1
BIT 0
PA1
PA0
I
I
IC2
IC3
—
—
NOTE
The timer forces the I/O state to output for each port A line associated with an en-
abled output compare. In these cases the data direction bits will not be changed,
but have no effect on these lines. The DDRA will revert to controlling data direction
when the associated timer compare is disabled. Input captures do not force either
the I/O state of the pin or the state of DDRA. To enable PA3 as fourth input capture,
set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth out-
put compare out of reset, with bit I4/O5 being cleared. If the DDA3 bit in DDRA is
set (configuring PA3 as an output), and IC4 is enabled, writes to PA3 cause edges
on the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/
O5 register is acting as IC4. PA7 drives the pulse accumulator input but also can
be configured for general-purpose I/O or output compare. DDA7 bit in DDRA reg-
ister configures PA7 for either input or output. Note that even when PA7 is config-
ured as an output, the pin still drives the pulse accumulator input.
MC68HC11EA9
28
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