MC68HC11EA9 Datasheet, PDF (23/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
Table 7 Interrupt and Reset Vector Assignments
FFDA, DB
Pulse Accumulator Input Edge
Bit I
PAII
17
FFDC, DD
Pulse Accumulator Overflow
Bit I
PAOVI
16
FFDE, DF
Timer Overflow
Bit I
TOI
15
FFE0, E1
Timer Input Capture 4/Output Compare 5
Bit I
I4/O5I
14
FFE2, E3
Timer Output Compare 4
Bit I
OC4I
13
FFE4, E5
Timer Output Compare 3
Bit I
OC3I
12
FFE6, E7
Timer Output Compare 2
Bit I
OC2I
11
FFE8, E9
Timer Output Compare 1
Bit I
OC1I
10
FFEA, EB
Timer Input Capture 3
Bit I
IC3I
9
FFEC, ED
Timer Input Capture 2
Bit I
IC2I
8
FFEE, EF
Timer Input Capture 1
Bit I
IC1I
7
FFF0, F1
Real-Time Interrupt
Bit I
RTII
6
FFF2, F3
IRQ (External Pin)
Bit I
None
5
FFF4, F5
XIRQ Pin
Bit X
None
4
FFF6, F7
Software Interrupt
None
None
*
FFF8, F9
Illegal Opcode Trap
None
None
*
FFFA, FB
COP Failure
None
NOCOP
3
FFFC, FD
Clock Monitor Fail
None
CME
2
FFFE, FF
RESET
None
None
1
* Same level as an instruction
OPTION — System Configuration Options
$1039
BIT 7
6
5
4
3
2
1
BIT 0
ADPU
CSEL
IRQE*
DLY*
CME
—
CR1*
CR0*
RESET:
0
0
0
1
0
0
0
0
* Can be written only once in first 64 cycles after reset in normal modes, or at any time in special modes.
ADPU — A/D Converter Power up
Refer to 9 Analog-to-Digital Converter
CSEL — Clock Select
Refer to 4.10 EEPROM.
IRQE — IRQ Select Edge-Sensitive Only
0 = IRQ input is active-low
1 = IRQ input recognizes falling edges only
DLY — Enable Oscillator Start-up Delay
0 = No stabilization delay on exit from STOP mode.
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU exits STOP mode.
CME — Clock Monitor Enable
0 = Clock monitor disabled; slow clock can be used.
1 = Slow or stopped clocks cause COP failure reset.
Bit 2 — Not implemented
Always reads zero
CR[1:0] — COP Timer Rate Select
Refer to the following table of COP timer rates.
MC68HC11EA9
MC68HC11EA9TS/D
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