MC68HC11EA9 Datasheet, PDF (29/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
DDRA — Port A Data Direction
RESET:
BIT 7
DDA7
0
6
DDA6
0
5
DDA5
0
4
DDA4
0
3
DDA3
0
2
DDA2
0
1
DDA1
0
BIT 0
DDA0
0
DDA[7:0] — Data Direction for Port A
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
PORTB — Port B Data
RESET:
Alt. Pin
Func.:
BIT 7
PB7
0
ADDR15
6
PB6
0
ADDR14
5
PB5
0
ADDR13
4
PB4
0
ADDR12
3
PB3
0
ADDR11
2
PB2
0
ADDR10
1
PB1
0
ADDR9
BIT 0
PB0
0
ADDR8
$1001
$1004
DDRB — Port B Data Direction
RESET:
BIT 7
DDB7
0
6
DDB6
0
5
DDB5
0
4
DDB4
0
DDB[7:0] — Data Direction for Port B
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
3
DDB3
0
2
DDB2
0
1
DDB1
0
BIT 0
DDB0
0
PORTC — Port C Data
RESET:
Alt. Pin
Func.:
Or:
BIT 7
PC7
0
ADDR7
DATA7
6
PC6
0
ADDR6
DATA6
5
PC5
0
ADDR5
DATA5
4
PC4
0
ADDR4
DATA4
3
PC3
0
ADDR3
DATA3
2
PC2
0
ADDR2
DATA2
1
PC1
0
ADDR1
DATA1
BIT 0
PC0
0
ADDR0
DATA0
$1006
$1003
PORTCL — Port C Latched Data
$1005
RESET:
BIT 7
PCL7
0
6
PCL6
0
5
PCL5
0
4
PCL4
0
3
PCL3
0
2
PCL2
0
1
PCL1
0
BIT 0
PCL0
0
PORTCL is used in the handshake clearing mechanism. When an active edge occurs on the STRA pin,
port C data is latched into the PORTCL register. Reads of this register return the last value latched into
PORTCL and clear STAF flag (following a read of PIOC with STAF set).
DDRC — Port C Data Direction
RESET:
BIT 7
DDC7
0
6
DDC6
0
5
DDC5
0
4
DDC4
0
3
DDC3
0
2
DDC2
0
1
DDC1
0
BIT 0
DDC0
0
$1007
DDC[7:0] — Data Direction for Port C
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
MC68HC11EA9
MC68HC11EA9TS/D
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