MC68HC11EA9 Datasheet, PDF (39/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
TMSK2 — Timer Interrupt Mask 2
$1024
BIT 7
6
5
4
3
TOI
RTII
PAOVI
PAII
—
RESET:
0
0
0
0
0
2
1
BIT 0
—
PR1
PR0
0
0
0
Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset in
normal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time.
TOI — Timer Overflow Interrupt Enable
If the TOI enable bit is set when the value in the timer counter register (TCNT) changes from $FFFF to
$0000, an interrupt is generated.
0 = Timer overflow interrupts disabled
1 = Interrupts are generated each time TCNT rolls over to $0000
RTII — Real-Time Interrupt Enable
If RTII enable bit is set, interrupts are generated at the rate determined by the real-time interrupt rate
(RTR[1:0]) bits in PACTL.
0 = Periodic interrupts are disabled
1 = Interrupts are generated at the rate determined by RTR[1:0]
PAOVI — Pulse Accumulator Overflow Interrupt Enable
If the PAOVI enable bit is set when the pulse accumulator counter register (PACNT) changes from
$FFFF to $0000 an interrupt is generated.
0 = PCNT overflow interrupts are disabled
1 = Interrupts are generated each time PCNT rolls over to $0000
PAII — Pulse Accumulator Input Edge Interrupt Enable
If the PAII enable bit is set when an edge (rising or falling, depending on configuration) is detected on
the pulse accumulator input pin (PA7/PAI), an interrupt is generated.
0 = Interrupts from edges on PAI pin are disabled
1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration)
Bits [3:2] — Not Implemented
Always read zero
PR[1:0] — Timer Prescaler Select
Table 16 Main Timer Prescaler Selection
PR1 PR0
0
0
0
1
1
0
1
1
Prescaler Selected
÷1
÷4
÷8
÷16
MC68HC11EA9
MC68HC11EA9TS/D
For More Information On This Product,
39
Go to: www.freescale.com