MC68HC11EA9 Datasheet, PDF (33/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
PLLCR — PLL Control
BIT 7
6
5
4
3
2
1
BIT 0
PLLON
BCS
AUTO
BWC
VCOT
MCS
LCK
WEN
RESET:
1
0
1
1
1
0
0
0
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PLLON — PLL System Enable
This bit activates the PLL synthesizer circuit without connecting its output to the control circuit. This al-
lows the synthesizer to stabilize before it can drive the CPU clocks. This bit resets to one, allowing the
synthesizer to stabilize as the device is being powered up.
0 = PLL is off
1 = PLL is on
BCS — Bus Clock Select
This bit determines which signal drives the clock circuitry generating the bus clocks. Refer to Figure 8.
Once BCS has been changed, up to 1.5 EXTAL cycles + 1.5 PLLOUT cycles may be required for the
transition. During the transition, all CPU activity will cease. BCS is cleared by a STOP or WAIT instruc-
tion or when V_DDSYN falls to the V_SS level.
0 = EXTAL drives the clock circuit
1 = VCOUT drives the clock circuit
NOTE
PLLON and BCS have built-in protection such that the PLL cannot be selected to
drive any clocks if the PLL is off. Similarly, the PLL cannot be turned off if it has
been selected as a clock source. Turning the PLL on and selecting its output as a
clock source require two separate writes to the PLLCR register.
AUTO — Automatic/Manual Loop Filter Bandwidth Control
This bit selects between automatic bandwidth control circuits within the phase detect block and manual
bandwidth control. Refer to Table 13.
0 = Automatic bandwidth control is selected
1 = Bandwidth control is manual
BWC — Loop Filter Bandwidth Control/Status
Bandwidth control is manual only when AUTO = 0. Since the low bandwidth driver is always enabled,
BWC determines if the high bandwidth driver is enabled. When AUTO = 1, BWC is a read-only status
bit that indicates which mode has been selected by the internal circuit. During PLL start-up in automatic
mode, the high bandwidth driver is enabled by internal circuitry until the PLL is near the selected fre-
quency. The high bandwidth driver is then disabled and BWC is cleared. Refer to Table 13.
0 = Only the low bandwidth driver is enabled
1 = Both low and high bandwidth drivers are selected
Table 13 Loop Filter Bandwidth Driver Control
AUTO BWC VCOT High Bandwidth Driver
0
0
0
Off
0
0
1
Off
0
1
0
On
0
1
1
On
1
X
1
Automatic
Low Bandwidth Driver
Off
On
Off
On
On
VCOT — Voltage Controlled Oscillator (VCO) Test
This bit is used to isolate the loop filter from the VCO to aid in factory testing of the PLL. VCOT is always
set when AUTO = 1 (automatic bandwidth control mode). This bit can be written only in special test
mode.
0 = Loop filter low bandwidth mode is disabled (factory test only)
1 = Loop filter operates according to values of AUTO and BWC control bits
MC68HC11EA9
MC68HC11EA9TS/D
For More Information On This Product,
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