MC68HC11EA9 Datasheet, PDF (10/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
4 Operating Modes and On-Chip Memory
4.1 Single-Chip Mode
In single-chip mode, ports B and C are available for general-purpose parallel I/O. Strobe pins A (STRA)
and B (STRB) can be used to control handshaking of parallel I/O on ports B and C. In this mode, all
software needed to control the MCU is contained in internal resources. ROM/EPROM (if present) will
always be enabled out of reset, ensuring that the reset and interrupt vectors will be available at locations
$FFC0–$FFFF.
4.2 Expanded Mode
In expanded operating mode, the MCU can access the full 64-Kbyte address space. The space includes
the same on-chip memory addresses used for single-chip mode as well as addresses for external pe-
ripherals and memory devices. The expansion bus is made up of ports B and C, and control signals AS
and R/W. R/W (read/write) and AS (address strobe) allow the low-order address and the 8-bit data bus
to be multiplexed on the same pins. During the first half of each bus cycle address information is
present. During the second half of each bus cycle the pins become the bidirectional data bus. AS is an
active-high latch enable signal for an external address latch. Address information is allowed through the
transparent latch while AS is high and is latched when AS drives low. Figure 5 shows an example of
address and data demultiplexing.
ADDR/DATA DEMUX
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
MCU
PC4
PC3
PC2
PC1
PC0
AS
R/W
E
DATA1
Q1
DATA2
Q2
DATA3
Q3
DATA4
Q4
DATA5
Q5
DATA6
Q6
DATA7
Q7
DATA8
Q8
LE
Q0
Figure 5 Address/Data Demultiplexing
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
WE
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
MC68HC11EA9
10
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MC68HC11EA9TS/D
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