MC68HC11EA9 Datasheet, PDF (32/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
7.1 Phase-Locked Loop Synthesizer
The phase-locked loop synthesizer (PLL) generates clocks for the CPU, bus circuitry, and A/D convert-
er. The clocks for the SCI and timers are derived directly from the EXTAL clock. The EXTAL clock also
provides the reference for the synthesizer which generates a frequency that is a multiple of the EXTAL
clock frequency. Values written to the SYNR register determine the factor by which the EXTAL clock is
scaled. Refer to Figure 8.
The PLL has two frequency bandwidths which are automatically selected whenever AUTO = 1 in the
PLLCR register. When the PLL is first enabled, the wide bandwidth is selected to provide a fast ramp
time. When the desired frequency is nearly reached, the low bandwidth is selected to provide greater
stability. Manual control of bandwidth can be accomplished by clearing the AUTO bit.
V_DDSYN
PIN
VDDSYN
EXTERNAL
CRYSTAL
XFC
PIN
EXTAL
PIN
XTAL
PIN
EXTAL
CRYSTAL
OSCILLATOR
XFC
PHASE
PCOMP
DETECT
LOOP FILTER
VCO
FREQUENCY
DIVIDER
VCOUT
EXTAL
VCOUT
PHASE-LOCKED
LOOP SYNTHESIZER
BUS
CLOCK
SELECT
BCS
0 = EXTAL
1 = VCOUT
MODULE
CLOCK
SELECT
MCS
0 = EXTAL
1 = 4XCLK
EA9 PLL BLOCK
4XCLK
FOR CPU
÷4
AND MEMORIES
TIMER
CLOCK
PLLMO
FOR SCI
÷4
AND TIMER
SCI
CLOCK
÷2
SYNCHRONIZE
WITH PH2
SYNR
2(Y + 1)•(2X)
Y = SYNY[1:0]
X = SYNX[5:0]
E
PH2
PLLTO
TO TIMER
PRESCALER
SCI BAUD CLOCK
TO SCI MODULUS
BAUD GENERATOR
Figure 8 Phase-Locked Loop Synthesizer Block Diagram
MC68HC11EA9
32
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