MC68HC11EA9 Datasheet, PDF (45/58 Pages) Motorola, Inc – 8 BIT HCMOS SINGLE CHIP MICROCONTOROLLER WITH A/D CONVERTER

Freescale Semiconductor, Inc.
PEDGE — Pulse Accumulator Input Edge Select
0 = Interrupts from edges on PAI pin are disabled
1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration)
Bit 3 — Not Implemented
Always reads zero
I4/O5 — Input Capture 4/Output Compare 5 Select
Refer to 7.2 Main Timer.
RTR[1:0] — Timer Prescaler Select
Refer to 7.3 Real-Time Interrupt.
PACNT — Pulse Accumulator Counter
$1027
BIT 7
6
5
4
3
2
1
BIT 0
BIT 7
6
5
4
3
2
1
BIT 0
Can be read and written, unaffected by reset.
TMSK2 — Timer Interrupt Mask 2
$1024
BIT 7
6
5
4
3
TOI
RTII
PAOVI
PAII
—
RESET:
0
0
0
0
0
2
1
BIT 0
—
PR1
PR0
0
0
0
Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset in
normal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time.
TOI — Timer Overflow Interrupt Enable
Refer to 7.2 Main Timer.
RTII — Real-Time Interrupt Enable
Refer to 7.3 Real-Time Interrupt.
PAOVI — Pulse Accumulator Overflow Interrupt Enable
If the PAOVI enable bit is set when the pulse accumulator counter register (PACNT) changes from
$FFFF to $0000 an interrupt is generated.
0 = PCNT overflow interrupts are disabled
1 = Interrupts are generated each time PCNT rolls over to $0000
PAII — Pulse Accumulator Input Edge Interrupt Enable
If the PAII enable bit is set when an edge (rising or falling, depending on configuration) is detected on
the pulse accumulator input pin (PA7/PAI), an interrupt is generated.
0 = Interrupts from edges on PAI pin are disabled
1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration)
Bits [3:2] — Not Implemented
Always read zero
PR[1:0] — Timer Prescaler Select
Refer to 7.2 Main Timer.
MC68HC11EA9
MC68HC11EA9TS/D
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