F81216AD Datasheet, PDF (6/43 Pages) Feature Integration Technology Inc. – LPC to 4 UART + 9-bit Protocol

F81216AD
4. Pin Description
I/O_8t5V-d100 - TTL level bi-directional pin with 8 mA source-sink capability, 5V tolerance, pull-down
100K ohms
I/O_12t
- TTL level bi-directional pin with 12 mA source-sink capability
I/OD₁₂
- TTL level bi-directional pin, Open-drain outpu with 12 mA sink capability
PCI_5V
OUT₁₂
- bi-direction pin, slew rate control, 5V tolerance.
- Output pin with 12 mA source-sink capability
OD₁₂
- Open-drain output pin with 12 mA sink capability
IN_t
- TTL level input pin
IN_t5V
- TTL level input pin and 5V tolerance.
IN_ts
IN_ts5V
- TTL level input pin and schmitt trigger
- TTL level input pin and Schmitt trigger, 5V tolerance.
P
- Power
4.1 ISA/LPC Interface
Pin No. Pin Name
1
PCIRST#
2
WDT_OUT#
4~7
LPC_LAD[3:0]
8
LCLK
9
FRAME#
10
SERIRQ
12
CLKIN
Type
IN_ts
OD₁₂
PCI_5V
IN_ts5V
IN_ts5V
PCI_5V
IN_t5V
Description
System PCI reset active low.
Watch dog timer output. When pin 24 power on setting
PS_WDT=0(default), Watch Dog timer time interval setting is
programmed by register. Once power on setting PS_WDT=1,
watch dog timer time interval will be fixed to 10 sec.
When in LPC mode, these signal lines communicate address,
control, and data information over the LPC bus between a host
and a peripheral.
In LPC mode, this pin acts as PCI clock input.
In LPC mode, indicates start of a new cycle or termination of a
broken cycle.
In LPC mode, Serial IRQ input/Output.
Clock Input
-3-
July, 2008
V0.20P