F81216AD Datasheet, PDF (37/43 Pages) Feature Integration Technology Inc. – LPC to 4 UART + 9-bit Protocol

6.6. Watchdog Timer Registers (CR08)
F81216AD
Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0 WDT_EN
R/W Default
Description
-
- Reserved
R/W 0 0: disable WDT.
1: enable WDT.
This bit is determined by DTR3#/PS_WDT. The power value will “1” if an
external pull up resistor is attached to DTR3#/PS_WDT. Otherwise, the power
on value will be “0”.
Base Address High Register  Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
Description
R/W - The MSB of UART 3 base address.
This byte is determined by DTR3#/PS_WDT. The power on default is 0x04 if
SOUT3/PS_3E8_IRQC is pull up. Otherwise, it is 0x00.
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
Description
R/W - The LSB of UART 3 base address.
This byte is determined by DTR3#/PS_WDT. The power on default is 0x42 if
DTR3#/PS_WDT is pull up. Otherwise, it is 0x00.
IRQ Channel Select Register  Index 70h
Bit
Name
7-5 Reserved
4 WDTIRQ_EN
3-0 SELWDTIRQ
R/W Default
Description
-
- Reserved.
R/W 0 ^{0 : Disable WDT IRQ.}
1 : Enable WDT IRQ.
R/W 0h Select the IRQ channel for WDT.
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July, 2008
V0.20P