F81216AD Datasheet, PDF (23/43 Pages) Feature Integration Technology Inc. – LPC to 4 UART + 9-bit Protocol

6.1.4 Chip ID Register  Index 21h
Bit
Name
R/W Default
7-0 CHIP_ID2
R 16h Chip ID2 of F81216AD.
F81216AD
Description
6.1.5 Vendor ID Register  Index 23h
Bit
Name
R/W Default
Description
7-0 VENDOR_ID1
R 19h Vendor ID 1 of Fintek devices.
6.1.6 Vendor ID Register  Index 24h
Bit
Name
R/W Default
Description
7-0 VENDOR_ID2
R 34h Vendor ID 2 of Fintek devices.
6.1.7 Clock Select Register  Index 25h
Bit
Name
R/W Default
Description
7-1 Reserved
0 CLK_SEL
-
- Reserved
R/W 0 ^{1 : The CLKIN is 48MHz}
0 : The CLKIN is 24MHz.
This bit must program to indicate the frequency of the clock source, or the
device will not function correctly.
6.1.8 Port SelectRegister  Index 27h
Bit
Name
R/W Default
Description
7-5 Reserved
-
- Reserved.
4 PORT_4E_EN
3-2 Reserved
-
- ^{The default value of this bit is decided by power on strap pin PS_CONF_2E.}
The default is “1” when PS_CONF_2E is low during power on.
0: The configuration port is 0x2E/0x2F.
1: The configuration port is 0x4E/0x4F.
-
- Reserved.
-20-
July, 2008
V0.20P