F81216AD Datasheet, PDF (26/43 Pages) Feature Integration Technology Inc. – LPC to 4 UART + 9-bit Protocol

5 RTS_Invert
4 RS485_URA
3 ^RXW4C_IRA
2 TXW4C_IRA
1-0 ^SELURACLK1
SELURACLK0
F81216AD
R/W 0 0: Default non function
1: When RS485_URA set to 1, RTS# signal will be inverted when assert out.
R/W 0 ^{0: RS232 mode}
1: RS485 mode, which will auto assert RTS# (RTS# is low) when receiving is
required..
R/W 0 ^{0 : No reception delay when SIR is changed from TX to RX.}
1 : Reception delay 4 character-time when SIR is changed from TX to RX.
R/W 0 ^{0 : No transmission delay when SIR is changed from RX to TX.}
1 : Transmission delay 4 character-time when SIR is changed from RX to TX.
R/W 00 ^{00: UART 1 clock source is 1.8462MHz ( 24MHz/13 )}
01: UART 1 clock source is 18MHz.
10: UART 1 clock source is 24MHz.
11: UART 1 clock source is 14MHz.
IR Control Register  Index F1h
Bit
Name
7-5 ^Reserved
4-3 ^IRA_MODE1
IRA_MODE0
2 ^{Half_Full_Duplex}
1 ^TXINV_IRA
0 RXINV_IRA
R/W Default
Description
R
- ^{Return 010b when read.}
R/W 00 ^{0X: Disable IR1 function.}
10 : Enable IR1 function, active pulse is 1.6uS.
11 : Enable IR1 function, active pulse is 3/16 bit time.
R/W 0 ^{0 : Full Duplex function for IR self test.}
1 : Half Duplex function.
Return 1 when read.
R/W 0 ^{0 : IRTX1 is not inversed.}
1 : Inverse the IRTX1.
R/W 0 ^{0 : IRRX1 is not inversed.}
1 : Inverse the IRRX1.
9-bit Mode Slave Address Register  Index F4h
Bit
Name
R/W Default
Description
-23-
July, 2008
V0.20P