F81216AD Datasheet, PDF (28/43 Pages) Feature Integration Technology Inc. – LPC to 4 UART + 9-bit Protocol

6.3. UART2 Registers (CR01)
F81216AD
UART 2 Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0 UR2_EN
R/W Default
Description
-
- Reserved
R/W - 0: disable UART 2.
1: enable UART 2.
This bit is determined by SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB.
The power value will “1” if an external pull up resistor is attached to
SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB. Otherwise, the power on
value will be “0”.
Base Address High Register  Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
Description
R/W - The MSB of UART 2 base address.
This byte is determined by SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB.
The power on default is 0x02 if SOUT2/PS_2F8_IRQB or
DTR2#/PS_2E0_IRQB is pull up. Otherwise, it is 0x00.
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
Description
R/W - The LSB of UART 2 base address.
This byte is determined by SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB.
The power on default is 0xF8 if SOUT2/PS_2F8_IRQB is pull up. It is 0xE0 if
DTR2#/PS_2E0_IRQB is pull up. Otherwise, it is 0x00.
IRQ Channel Select Register  Index 70h
Bit
Name
7-6 Reserved
R/W Default
-
- Reserved.
Description
-25-
July, 2008
V0.20P