F81216AD Datasheet, PDF (22/43 Pages) Feature Integration Technology Inc. – LPC to 4 UART + 9-bit Protocol

F81216AD
61
Base Address Low Register
1/0 1/0 1/0 0 1/0 0 0 0
70
IRQ Channel Select Register
- - 0 0 1/0 0 0 1/0
F0
Clock Select Register
00000000
F4
9-bit Mode Slave Address Register
00000000
F5
9-bit Mode Slave Address Mask Register
00000000
Register
0x[HEX]
30
WDT Device Configuration Registers (LDN CR08)
Register Name
MSB
Default Value
UART2 Device Enable Register
------
LSB
- 1/0
60
Base Address High Register
0 0 0 0 0 1/0 0 0
61
Base Address Low Register
0 1/0 0 0 0 0 1/0 0
70
IRQ Channel Select Register
- - - 00000
F0
Timer Status and Control Register
- - - - - 0 1/0 0
F1
Timer Count Number Register
0 0 0 0 1/0 0 0 1/0
6.1. Global Control Registers
6.1.1 Software Reset Register  Index 02h
Bit
Name
R/W Default
Description
7-1 Reserved
0 SOFT_RST
-
- Reserved
R/W 0 Write 1 to reset the register and device powered by VDD ( VCC ).
6.1.2 Logic Device Number Register (LDN)  Index 07h
Bit
Name
R/W Default
Description
7-0 LDN
R/W 00h 00h : Select UART 1 device configuration register
01h : Select UART 2 device configuration register
02h : Select UART 3 device configuration register
03h : Select UART 4 device configuration register
08h : Select Watchdog Timer device configuration register
6.1.3 Chip ID Register  Index 20h
Bit
Name
R/W Default
7-0 CHIP_ID1
R 02h Chip ID 1 of F81216AD..
Description
-19-
July, 2008
V0.20P