F81216AD Datasheet, PDF (14/43 Pages) Feature Integration Technology Inc. – LPC to 4 UART + 9-bit Protocol

5:3 Reserved
2
CLRTX
1
CLRRX
0
FIFO_EN
11 : Receiver FIFO trigger level is 14.
W
W
1 : Reset the transmitter FIFO.
W
1 : Reset the receiver FIFO.
W
0 : Disable FIFO
1 : Enable FIFO
F81216AD
5.2.1.8 Line Control Register – Base + 3
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7
DLAB
R/W 0 : Divisor Latch can’t be accessed.
1 : Divisor Latch can be accessed via Base and Base+1.
6
SETBRK
R/W 1 : Transmit a break condition.
0 : Transmitter is in normal condition.
5:3 STKPAR
R/W XX0 : Parity Bit is disable
EPS
001 : Parity Bit is odd.
PEN
011 : Parity Bit is even
101 : Parity Bit is logic 1
111 : Parity Bit is logic 0
2
STB
R/W 0 : Stop bit is one bit
1 : When word length is 5 bit stop bit is 1.5 bit
else stop bit is 2 bit
1:0 WLS[1:0]
R/W 00 : Word length is 5 bit
01 : Word length is 6 bit
10 : Word length is 7 bit
11 : Word length is 8 bit
5.2.1.9 MODEM Control Register – Base + 4
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:5 Reserved
R/W Return 0 when read.
4
LOOP
R/W 0 : UART in normal condition.
1 : UART is internal loop back
-11-
July, 2008
V0.20P