F81216AD Datasheet, PDF (31/43 Pages) Feature Integration Technology Inc. – LPC to 4 UART + 9-bit Protocol

6.4. UART3 Registers (CR02)
F81216AD
UART 3 Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0 UR3_EN
R/W Default
Description
-
- Reserved
R/W - 0: disable UART 3.
1: enable UART 3.
This bit is determined by SOUT3/PS_3E8_IRQC. The power value will “1” if an
external pull up resistor is attached to SOUT3/PS_3E8_IRQC. Otherwise, the
power on value will be “0”.
Base Address High Register  Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
Description
R/W - The MSB of UART 3 base address.
This byte is determined by SOUT3/PS_3E8_IRQC. The power on default is
0x03 if SOUT3/PS_3E8_IRQC is pull up. Otherwise, it is 0x00.
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
Description
R/W - The LSB of UART 3 base address.
This byte is determined by SOUT3/PS_3E8_IRQC. The power on default is
0xE8 if SOUT3/PS_3E8_IRQC is pull up. Otherwise, it is 0x00.
IRQ Channel Select Register  Index 70h
Bit
Name
7-6 Reserved
5 URCIRQ_MODE
R/W Default
Description
-
- Reserved.
R/W 0 ^{0 : PCI IRQ sharing mode.}
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
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July, 2008
V0.20P