F81216AD Datasheet, PDF (17/43 Pages) Feature Integration Technology Inc. – LPC to 4 UART + 9-bit Protocol

F81216AD
Two is programmed by registers.
The other is set the base address into registers, and use the base address the control it.
The timer unit has three kinds: 10mS, 1S, 1Min.
5.4.1 Watchdog Port Register
5.4.1.1 Timer Status and Control Register – Base + 0
Power-on default [7:0] = 0x02 when DTR3#/PS_WDT is pull-up, else 0x0.
Bit
Name
R/W
Description
7:3 Reserved
R/W Return 0 when read.
2:1 WDT_UNIT[1:0] R/W 00 : Timer Unit is 10ms.
01 : Timer Unit is 1 second
10 : Timer Unit is 1 minute.
11 : reserved.
0
WDT_EVENT
R/W When read
0 : no time out occur.
1 : time out has occurred.
when write
0 : no action
1 : clear the time out status.
5.4.1.2 Timer Count Number Register – Base + 1
Power-on default [7:0] = 0x0Ah when DTR3#/PS_WDT is pull-up , else 0x00h.
Bit
Name
R/W
Description
7:0 WDT_CNT[7:0]
R/W The number of count for watchdog timer.
Write the same value to enable the timer, write 0 to disable timer.
5.5 Serial IRQ
F81216AD supports a serial IRQ scheme. Because more than one device may need to
share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is
the PCI clock. The serial interrupt is transferred on the SERIRQ signal, one cycle consisting of
three frames types: a start frame, several IRQ/Data frame, and one Stop frame.
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July, 2008
V0.20P