F81216AD Datasheet, PDF (25/43 Pages) Feature Integration Technology Inc. – LPC to 4 UART + 9-bit Protocol

F81216AD
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
Description
R/W - The LSB of UART 1 base address.
This byte is determined by SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA.
The power on default is 0xF8 if SOUT1/PS_3F8_IRQA is pull up. It is 0xE0 if
DTR1#/PS_3E0_IRQA is pull up. Otherwise, it is 0x00.
IRQ Channel Select Register  Index 70h
Bit
Name
7-6 Reserved
5 URAIRQ_MODE
4 URAIRQ_SHAR
3-0 SELUR1IRQ
R/W Default
Description
-
- Reserved.
R/W 0 ^{0 : PCI IRQ sharing mode.}
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
R/W 0 ^{0 : IRQ is not sharing with other device.}
1 : IRQ is sharing with other device.
R/W - Select the IRQ channel for UART 1.
This byte is determined by SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA.
The power on default is 0x03 if SOUT1/PS_3F8_IRQA or
DTR1#/PS_3E0_IRQA is pull up. Otherwise, it is 0x00.
RS485 Enable Register  Index F0h
Bit
Name
R/W Default
Description
7 ^{9BIT_MODE_URA} R/W
6 AUTO_ADDR_URA R/W
0 ^{0: normal UART function}
1: enable 9-bit mode (multi-drop mode).
In the 9-bit mode, the parity bit becomes the address/data bit..
0 ^{This bit works only in 9-bit mode.}
0: the SM2 bit will be cleared by host, so that data could be received.
1: the SM2 bit will be cleared by hardware according to the sent address and
the given address (or broadcast address derived by SADDR_URA and
SADEN_URA)
-22-
July, 2008
V0.20P