FMS9875 Datasheet, PDF (9/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

FMS9875
PRODUCT SPECIFICATION
Functional Description
There are two major sections within the FMS9875:
1. Analog-to-digital Converter Channels, one for each
channel, GY, RP, BP and the voltage reference.
2. Timing and Control comprising the PLL, Timing
Generator, Sync Stripper and Serial Interface.
A/D Converter Channels
Each of the RGB/YP_BP_R channels consists of:
1. A clamp to set the lower reference of each G/Y, B and R
channel or the midpoint reference of the P_B and P_R
channels.
2. Gain and offset stages to match the A/D converter range
to input signal levels.
3. An Analog-to-Digital Converter to digitize the analog
input.
A plot of output codes versus input voltage has a staircase-
like shape. With FMS9875 Gain and Offset register values
set to match a nominal 700 mV input, Tables 1 and 2 show
the output codes in deciminal and binary, corresponding to
the mid-point input voltages of each step.
Note:
1. The midpoint of code 000 lies 1/2 of one code-size
below the 000/001 transition.
2. The midpoint of code 255 lies 1/2 of one code-size
above the 254/255 transition.
3. For AC coupled inputs, during the blanking period:
a) Y, G, B and R inputs should be clamped to the
FMS9875 bottom reference.
b) P_B and P_R inputs should be clamped to the FMS9875
mid-range level. (Half the range plus the offset
voltage)
Table 1. YP_BP_R and GBR Decimal Output Coding
Input (mV)
Y, G, B, R
P_B, P_R
Offset Binary Two’s Complement
700
255
255
127
697.25
254
254
126
351.37
128
128
000
348.63
127
127
255
345.88
126
126
254
2.75
001
001
129
0
000
000
128
Table 2. YP_BP_R and GBR Binary Output Coding
Input (mV)
350 mV ref. 0 mV ref.
Y, G, B, R
P_B, P_R
Offset Binary Two’s Complement
700
350
1111 1111 1111 1111
0111 1111
697.25
347.25 1111 1110 1111 1110
0111 1110
351.37
348.63
345.88
1.37
-1.37
-4.12
1000 0000
0111 1111
0111 1110
1000 0000
0111 1111
0111 1110
0000 0000
1111 1111
1111 1110
2.75
-347.25 0000 0001 0000 0001
0
-350
0000 0000 0000 0000
1000 0001
1000 0000
REV. 1.2.15 1/14/02
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