FMS9875 Datasheet, PDF (3/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

FMS9875
PRODUCT SPECIFICATION
Phase Locked Loop
With a horizontal sync signal connected to the HSIN input
pin, the PLL generates a high frequency internal clock sig-
nal, PXCK that is fed to the Timing and Control logic. Fre-
quency of PXCK is set by the register programmable PLL
divide ratio, PLLN.
COAST is an input that disables the PLL lock to the horizon-
tal sync input, HSIN. If HSIN is to be disregarded for a
period such as the vertical sync interval, COAST allows the
VCO frequency to be maintained. Missing horizontal sync
pulses during the vertical interval can cause tearing at the top
of a picture, if COAST is not used.
Two pixels per clock mode is set by programming the PLL
to half the pixel rate. By toggling the INVCK pin between
frames, even and odd pixels can be read on alternate frames.
Serial Interface
Registers are accessed through an I²C/SMBus compatible
serial port. Four serial addresses are pin selectable.
Pin Assignments
100-Lead MQFP (KG)
DYG (7)
76
DYG (6)
77
DYG (5)
78
DYG (4)
79
DYG (3)
80
DYG (2)
81
DYG (1)
82
DYG (0)
83
GND
84
VDDO
85
DCK
86
DCK
87
HSOUT
88
DCSOUT
89
GND
90
VDDO
91
GND
92
GND
93
GND
94
VDDA
95
PWRDNB
96
REFOUT
97
REFIN
98
VDDA
99
VDDA
100
50
VDDO
49
GND
48
NC
47
NC
46
NC
45
NC
44
NC
43
NC
42
GND
41
GND
40
GND
39
VDDP
38
GND
37
VDDP
36
GND
35
LPF
34
XCK
33
VDDP
32
GND
31
COAST
30
HSIN
29
GND
28
GND
27
VDDP
26
VDDP
REV. 1.2.15 1/14/02
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