FMS9875 Datasheet, PDF (24/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

PRODUCT SPECIFICATION
FMS9875
PLL Performance Characteristics
Parameter
Temp.
Clock Input
t_JPP Peak-to-peak PLL Jitter
MHz
31.5
25°C
49.5
78.75
108
135
t_JRMS RMS Jitter
MHz
31.5
25°C
49.5
78.75
108
135
t_J2PP
Peak-to-peak jitter with
subdivide ratio equal
to 2.
MHz
31.5
49.5
25°C
t_J2RMS RMS jitter with subdivide
ratio equal to 2.
MHz
31.5
25°C
49.5
Notes
1. In Figures 21-23, the dashed curve is with subdivide ratio = 2.
Test
Rank
C
C
C
C
Min. Typ. Max. Unit
ps
6000
3117
1493
892
750
ps
873
488
245
148
122
ps
1600
1700
ps
330
203
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0 20 40 60 80 100 120 140 160
VCO Frequency, MHz
Figure 21. Pixel Clock Peak-to-Peak Jitter
1400
1200
1000
800
600
400
200
0
0 20 40 60 80 100 120 140 160
VCO Frequency, MHz
Figure 22. Pixel Clock RMS Jitter
5%
4%
3%
2%
1%
0
0 20 40 60 80 100 120 140 160
VCO Frequency, MHz
Figure 23. Pixel Clock % RMS Jitter
24
REV. 1.2.15 1/14/02