FMS9875 Datasheet, PDF (1/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

www.fairchildsemi.com
FMS9875
GBR YP_BP_R Graphics Digitizer
Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL
Features
• 108/140 Ms/s conversion rate
• RGB and YP_BP_R clamps
• 444 and 422 output timing
• Adjustable Gain and offset
• Internal Reference Voltage
• I²C/SMBus compatible Serial Port
• 100-pin package
Applications
• YP_BP_R Digitizers
• Projectors
• TV sets
Description
As a fully integrated graphics interface, the FMS9875 can
digitize RGB or YP_BP_R video signals at resolutions up to
1280 x 1024 with 75 Hz refresh rate. Compatible video
formats include NTSC-601, PAL-601, SMPTE 293M,
SMPTE 296M and SMPTE 274M.
Block Diagram
GY_IN
GY_REF
Bottom
Clamp
Gain &
Offset
The ADC sampling clock can be derived from either an
external source or from incoming horizontal sync using the
internal PLL. Setup and control is via registers accessible
through an SMBus/I²C compatible serial port.
Input amplitude range is 500–1000mV with either DC or AC
coupling. AC coupled inputs can be clamped to program-
mable midpoint/bottom levels or to external reference levels
using either internal or externally generated clamp timing.
Common to the three channels are clamp pulses, a bandgap
reference voltage and clocks derived from the HSYNC PLL
or an external clock source. Digital data output levels are
2.5–3.3V CMOS compliant.
Power is derived from a single +3.3 Volt power supply. Package
is a low cost 100-lead MQFP. Performance specifications are
guaranteed over 0°C to 70°C.
Product Number
FMS9875KAC100
FMS9875KAC140
Speed
108 Ms/s
140 Ms/s
A/D
DGY_7-0
BP_IN
BP_REF
Bottom/
Midpoint
Clamp
Gain &
Offset
A/D
444/422
DBP_7-0
RP_IN
RP_REF
Bottom/
Midpoint
Clamp
VREFIN
CLAMP
INVSCK
XCK
HSIN
COAST
LPF
SDA
SCL
A₀
A₁
PWRDN
Gain &
Offset
ICLAMP
A/D
444/422
DRP_7-0
SCK ^Reference
VREFOUT
Timing
Generator
HS
PLL
PXCK
ICLAMP
DCK
DCK
HSOUT
Control
ACS_IN
SYNC
Stripper
DCS_OUT
REV. 1.2.15 1/14/02