FMS9875 Datasheet, PDF (16/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

PRODUCT SPECIFICATION
FMS9875
Timing and Control
Timing and Control logic encompasses the PLL, Timing
Generator and Sync Stripper.
Phase Locked Loop
HSIN
Θi
Phase
Detector
V_DDP
C2
C1
R
Charge ^IP ^VZ VCO Θo
Pump
K_V
Sub-
divider
Θo /N
Divider
Two clock types originate in the PLL:
SCK
(DCK)
1. Data clocks DCK and DCK.
2. Internal sampling clock SCK.
DCK and DCK are used to strobe data from the FMS9875 to
following digital circuits. SCK is the ADC sample clock
which has adjustable phase controlled through the PHASE
register. DCK and DCK are phase aligned with SCK.
Reference for the PLL is the horizontal sync input, HSIN
with polarity selected by the HSPOL bit.
Frequency of the HS_IN input is multiplied by the value PLLN
+ 1 derived from the PLLN_11-4 and PLLN_3-0 registers. PLLN
+ 1 should equal the number of pixels per horizontal line
including active and blanked sections. Typically blanking is
20–30% of active pixels. Divide ratios from 2–4095 are
supported. SCK, DCK and DCK run at a rate PLLN + 1
times the HS_IN frequency.
The PLL consists of a phase comparator, charge pump VCO
and ÷N counter, with the charge pump connected through the
LPF pin to an external filter. These elements must be pro-
grammed to match the incoming video source to be captured.
Values of IPUMP and FVCO for common video standards
timing are shown in Table 7. Timing of many computer video
outputs does not comply with VESA recommendations.
PLLN should be optimized to avoid vertical noise bars on the
displayed image.
Modes marked 2X are 2X-oversampled modes where the
number of samples per horizontal line is doubled. To select
this mode, the Phase-locked Loop Divide Ratio value must
changed from PLL_1x to:
PLL_2x = 2 • (PLL_1x + 1) – 1
Table 7. Recommended IPUMP and FVCO values for Standard Display Formats
Standard
NTSC-601
PAL-601
Test
Rank Resolution
C 720 x 483i (1X)
C 720 x 583i (1X)
Refresh
Rate
30 Hz
25 Hz
Horizontal
Frequency
15.734 kHz
15.625 kHz
Sample Rate FVCO_1-0
13.5 MHz
00
13.5 MHz
00
IPUMP_2-0
101
101
SUBDIV_1-0
2
NTSC-601
C 720 x 483i (2X) 30 Hz 15.734 kHz
27 MHz
00
101
1
PAL-601
C 720 x 583i (2X) 25 Hz 15.625 kHz 27 MHz
00
101
SMPTE 293M C
720 x 483p
60 Hz 31.4685 kHz 27 MHz
00
111
2
SMPTE 296M C 1280 x 720p 60 Hz 45.00 kHz 74.25 MHz
01
111
1
SMPTE 274M C 1920 x 1080i 30 Hz 33.750 kHz 74.25 MHz
01
111
VGA
C
640 X 480
60 Hz
31.5 kHz 25.175 MHz 01
110
C
75 Hz
37.5 kHz 31.500 MHz
01
110
2
C
85 Hz
43.3 kHz 36.000 MHz
01
110
SVGA
C
800 X 600
60 Hz
37.9 kHz 40.000 MHz 01
110
C
75 Hz
46.9 kHz 49.500 MHz
01
110
1
CT
85 Hz
53.7 kHz 56.250 MHz
01
110
XGA
C
1024 X 768 60 Hz
48.4 kHz 65.000 MHz
10
110
C
75 Hz
60.0 kHz 78.750 MHz
10
110
1
C
85 Hz
68.3 kHz 94.500 MHz
11
110
SXGA
C 1280 X 1024 60 Hz
64.0 kHz 108.000 MHz 11
110
CT
72 Hz
78.1 kHz 135.000 MHz 11
111
1
CT
75 Hz
80.0 kHz 135.000 MHz 11
111
Notes:
1. VESA Monitor Timing Standards and Guidelines, September 17, 1998 and others.
2. Frame refresh rate is twice the field refresh rate for interlace (i) formats and equal to the field rate for progressive (p) formats.
3. When SUBDIV_1-0 = 2, VCO runs at 2x sample rate.
16
REV. 1.2.15 1/14/02