FMS9875 Datasheet, PDF (5/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

FMS9875
PRODUCT SPECIFICATION
Pin Descriptions
Pin
Name
Pin No.
Power and Ground
V_DDA
V_DDP
5, 7, 11, 13, 17, 19, 95, 99, 100
26, 27, 33, 37, 39
V_DDO
50, 60, 62, 72, 85, 91
GND
V_REFIN
1, 6, 8, 12, 14, 18, 28, 29, 32, 36, 38, 40,
41, 42, 49, 59, 61, 71, 84, 90, 92, 93, 94
98
V_REFOUT
97
Pin Function Description
ADC Supply Voltages. Provide a quiet noise free voltage.
PLL Supply Voltage. Most sensitive supply voltage.
Provide a very quiet noise free voltage.
Digital Output Supply Voltage. Decouple judiciously to
avoid propagation of switching noise.
Ground. Returns for all power supplies. Connect ground
pins to a solid ground-plane.
Voltage Reference Input. Common reference input to
RGB converters. Connect to VREFOUT, if internal
reference is used.
Voltage Reference Output. Internal band-gap reference
output. Tie to ground through a 0.1µF capacitor.
Addressable Memory
Register Map
Name
PLLN_11-4
PLLCTRL
GGY_7-0
GBP_7-0
GRP_7-0
OSGY_5-0
OSBP_5-0
OSRP_5-0
CD_7-0
CW_7-0
CONFIG 1
Address
00
01
02
03
04
05
06
07
08
09
0A
Function
PLL divide ratio, MSBs. PLLN + 1 = total number of
pixels per horizontal line.
PLL Control Register.
1. Lower four bits of PLL divide ratio.
2. PLL Subdivide phase.
3. PLL Subdivide ratio.
Gain, green/luminance channel. Adjustable from 70 to
140%.
Gain, blue/P_B channel. Adjustable from 70 to 140%.
Gain, red/P_R channel. Adjustable from 70 to 140%.
Offset, green/luminance channel. OSR_5-0 is stored in
the six upper register bits 7-2. Default value is decimal 32.
OSGY_5–0 X X
Offset, blue/P_B channel. OSR_5-0 is stored in the six
upper register bits 7-2. Default value is decimal 32.
OSBP_5–0 X X
Offset, red/P_R channel. OSR_5-0 is stored in the six upper
register bits 7-2. Default value is decimal 32.
OSRP_5–0 X X
Clamp delay. Delay in pixels from trailing edge of
horizontal sync.
Clamp width. Width of clamp pulse in pixels.
Configuration Register No. 1
Default (hex)
69 (1693)
D0 (1693)
80
80
80
80
80
80
80
80
F4
REV. 1.2.15 1/14/02
5