FMS9875 Datasheet, PDF (11/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

FMS9875
Gain
G_7-0
Register
V_REF
D/A
PRODUCT SPECIFICATION
Offset
Register
OS_5-0
Current
D/A
I_BIAS + I_OFFSET
V_IN
R_LEVEL
A/D Core
+
Track &
Hold
A/D
-
SCK
D_7-0
Figure 2. A/D Converter Architecture
Within the A/D converter core are the following elements:
1. Differential track and hold.
2. Differential analog-to-digital converter.
Voltage offset from the common mode voltage at the invert-
ing input of the Track and Hold is:
V_OS
=
( OS_5–0
– 31) •
2----5---5----+-----G----_{7---–--0---}
255
• ^5----0---0-
255
Setting the gain register value G_7-0 (GRP_7-0, GGY_7-0, GBP_7-0),
establishes the gain D/A converter voltage which is the upper
A/D reference voltage. Increasing the gain register value
reduces the output level. Conversion range is defined by the gain
setting according to Table 5.
Table 5. Gain Calibration
G_7-0
Conversion Range (mV)
0
500
102
700
255
1000
A/D Converter sensitivity is:
S = ^2----5---5- • -----------2---5---5----------- LSB ⁄ mV
500 255 + G_{7 – 0}
Offset is set through the Track and Hold, which translates the
ground referenced input to a differential voltage centered
around A/D common mode bias voltage.
The 6-bit Offset D/A converter injects a current into R_LEVEL
with two components:
1. I_BIAS to establish the A/D common mode voltage.
2. I_OFFSET to set the offset from the common mode level.
D/A converter gain tracks A/D gain with 1 LSB of offset
corresponding to 1LSB of gain. Increasing the offset of a
video signal increases brightness of the picture. Data output
from the A/D converter is:
D_7–0 = S • V_IN – ( OS_5–0 – 31 )
Impact of the offset values OSGY_5-0, OSBP_5-0, and OSRP_5-0
is shown in Table 6.
Table 6. Offset Calibration
OS_5-0
0
31
63
Equivalent Offset (bits)
-31_d
0
32_d
Sampling Clock PHASE Adjustment
Bandwidth of TV video is typically well below the horizon-
tal sampling rate. Consequently, PHASE has little impact on
images sampled in the YP_BP_R format or RGB signals derived
from a video source. By contrast, PC-generated image
quality is strongly impacted by the PHASE_4-0 value. If
PHASE is not set correctly, any section of an image
consisting of vertical lines may exhibit tearing.
Figure 3 shows how an analog input, V_IN is sampled by the
rising edge of SCK after a delay PHASE from the rising
edge of either PXCK or XCK. SCK can be delayed up to 32
steps in 11.25° increments by adjusting the register value,
PHASE_4-0.
REV. 1.2.15 1/14/02
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