FMS9875 Datasheet, PDF (13/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

FMS9875
PRODUCT SPECIFICATION
HSIN
PXCK/XCK
PHASE
N
SCK
GBRIN/YPBPRIN
P0
DCK
DCK
D[7..0]
t_SKEW
D0
HSOUT
Figure 7. Output Timing
Figures 8 through 12 depict data output timing relative to the
sampling clock and inputs for all modes. Timing is referenced
to the leading edge of HSIN when the first sample is taken at
the rising edge of SCK. Register bit OUTPHASE, determines
if odd or even samples are directed to the data ports.
Note the timing of the HSOUT waveform:
1. HSOUT is always active HIGH.
2. Leading edge of HSOUT is aligned to the leading or
trailing edge (selected by the HSPOL register bit) of
HSIN delayed by 5 to 5.5 pixels
3. Leading edge is aligned with DCK.
4. Trailing edge is linked to HSIN.
5. If HSIN does not terminate before mid-line, HSOUT is
forced low. A 50% duty cycle indicates that HSPOL is
incorrectly set.
HS is the internal sync pulse generated from HSIN. SCK is
the internal A/D converter sampling clock.
Pixel sampling is referenced to the rising edge of HSIN.
Data outputs are delayed by 5 to 5.5 pixels. To allow for
clamping, start-of-active-video (SAV) can begin any time
after the falling edge of HSIN. End-of-active-video (EAV)
follows SAV any time before the next HSIN pulse.
GBRIN
HSIN
PXCK
HS
SCK
DCK
DGBR _7-0
HSOUT
P0 P1 P2 P3 P4 P5 P6 P7
5 PIXEL DELAY
D0 D1 D2 D3 D4 D5 D6 D7
Figure 8. GBR Mode
REV. 1.2.15 1/14/02
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