FMS9875 Datasheet, PDF (25/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

FMS9875
PRODUCT SPECIFICATION
Applications Information
For additional applications information see Applications
Notes available from the factory.
To minimize component count, use of the following on-chip
circuits is recommended:
1. ADC sampling clock.
2. Clamp.
3. Voltage reference
Optimum PLL Configuration Register (address 0x0C)
settings for typical modes are listed in Table 7. Unless
otherwise indicated, all modes are compliant with VESA or
SMPTE specifications. For unlisted modes, values should be
adjusted to optimize performance.
By adjusting the values in the gain (GRP, GGY, GBP) and
offset (OSRO, OSGY, OSBP) registers, the input conversion
range can be matched to the incoming analog signals.
AC Coupled Digitizer
Shown in Figure 24 is an implementation of a video digitizer
with AC coupled YP_BP_Rinputs. Horizontal sync input.
Output data is three channel 24-bit pixels with a maximum
rate of 140Ms/s. Data is clocked out on the negative edge of
DCK. HSOUT is delayed HSIN.
Control is through the serial port with 150Ω resistors
inserted to allow interfacing with 5V logic. If the serial bus is
operates with 3.3V levels, these resistors are unnecessary.
C1
VPLL
Y
.047uF
C2
R1
PB
75
.047uF
R2
F
75
SDA
SCL
F
PR
R4
150
R5
150
R3
75
C3
.047uF
F
INVSCK
CLAMP
VPLL
C4
R6
0.039uF 3.3k
C5
A0
A1
HSIN
0.0039uF
U1
FMS9875
26
27
33
37
39
VDDP
VDDP
VDDP
VDDP
VDDP
3 _YGIN
9 _BPIN
15 _RPIN
4 _YGREF
10 _BPREF
16 _RPREF
20 _CKINV
21 _CLAMP
22 _SDA
23 _SCL
24 _A0
25 _A1
30 _HSIN
31 _COAST
34 _XCK
35 _LPF
2 _ACSIN
96 _PWRDN
98 _REFIN
VADC
VDIG
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
75
74
73
48
47
46
45
44
43
DYG7
DYG6
DYG5
DYG4
DYG3
DYG2
DYG1
DYG0
76
77
78
79
80
81
82
83
DPB7
DPB6
DPB5
DPB4
DPB3
DPB2
DPB1
DPB0
63
64
65
66
67
68
69
70
DPR7
DPR6
DPR5
DPR4
DPR3
DPR2
DPR1
DPR0
51
52
53
54
55
56
57
58
DCK ⁸⁶
DCK ⁸⁷
HSOUT ⁸⁸
DCSOUT ⁸⁹
REFOUT ⁹⁷
RN1
16
15
14
13
12
11
10
9
RN3
16
15
14
13
12
11
10
9
100
1
2
3
4
5
6
7
8
RN2
16
15
14
13
12
11
10
9
100
1
2
3
4
5
6
7
8
100
1
2
3
4
5
6
7
8
R8
47
YDATA [7..0]
PBATA [7..0]
PRATA [7..0]
R7
47
DCK
DCK
F
REFOUT
C6
0.1uF
Figure 24. Schematic, VGA Digitizer, AC Coupled RGB
REV. 1.2.15 1/14/02
25