FMS9875 Datasheet, PDF (27/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

FMS9875
Pins 26, 27
C1
0.01µF
PRODUCT SPECIFICATION
Pin 33
C2
0.1µF
VADC Pins
VDD Pins
Pin 37
Pin 39
C3
0.01µF
C4
0.1µF
L1
VPLL ^BEAD
C5
10 µF
L2
BEAD
U1
RC1117-3.3
2 _OUT
4 _OUT
ADJ/GND
IN
3
C6
1
0.1µF
C8 C9 C10 C11 C12 C13 C14 C15
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
+ C24
10 µF
C16 C17 C18 C19 C20 C21 C22
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
L3
BEAD
U2
RC1117-3.3
2
4
OUT
OUT
ADJ/GND
IN
3
+ _C25
1
10µF
C23
0.1µF
Power Input
+ ^C7
10µF
Figure 26. Recommended Power Distribution
Physical placement of PLL power supply decoupling
components is critical. Bearing in mind the following
suggestions:
1. All components should be placed in close proximity to
the FMS9875 pins.
2. Routing through vias should be avoided, if possible.
3. Each V_DDP/GND pin pair: 26&27/28, 33/32, 37/38, and
39/40 should be decoupled with a either a 0.01 or 0.1 µF
capacitor (see Figure 24).
4. Use Fair-rite 274 301 9447 bead.
Firmware
Best performance can be achieved by correctly setting the
FMS9875 registers. Here are some recommendations:
1. For analog video, the sampling rate is usually 2X–3X
the video bandwidth. PLLN and PHASE are not critical.
2. For PC video, set the value of PLLN equal to the num-
ber of pixels to be sampled minus one. With this setting,
the number of samples per horizontal line equals the
number of pixels. If PLLN + 1 does not equal the num-
ber of pixels, there will be irregular intensities on text
and an interference pattern on a vertical grill pattern.
3. In the GBR mode, calibrate Offset and Gain by first set-
ting each input to 0mV. Then adjust OSGY, OSBP, and
OSRP to set each RGB data output D_7-0 = 0x00. Next
REV. 1.2.15 1/14/02
with 700mV input, adjust GGY, GBP and GRP so that
each RGB data output D_7-0 = (same value), typically
240 decimal. Average values during calibration to
minimize the impact of noise.
4. In the YP_BP_R mode, the Y-channel calibration procedure
is the same as for GBR. P_BP_R channels must be
calibrated differently. If the internal mid-scale clamp is
used, Offset is automatically preset. Only the Gain need
be adjusted to accomodate the swing from peak blue to
peak orange on the P_B channel; and peak red to peak
cyan onthe P_R channel. Average values during calibra-
tion to minimize the impact of noise.
5. Clamp registers, CD and CW, should be programmed to
maximize the period of the clamp during the backporch,
while not encroaching into the sync or active video
periods.
6. PHASE must be trimmed to minimize onscreen snow
(intensity noise) when a vertical grill pattern is
displayed.
7. FVCO must be set to encompass the incoming
frequency range.
8. IPUMP must be set to minimize intensity noise.
9. To ensure correct power-on defaults, program all regis-
ters including Test Register 0x0F, which must be set to
0x00 for normal operation. Note that unlike registers
0x00 through 0x0D, register 0x0F does not acknowl-
edge. The ACK bit remains H instead of being pulled L.
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