FMS9875 Datasheet, PDF (6/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

PRODUCT SPECIFICATION
FMS9875
Name
PHASE_7-0
PLLCTRL
CONFIG 2
Address
0B
0C
0D
0E
0F
Function
Sampling clock phase. PHASE_4-0 stored in upper
register bits 7-3. PHASE sets the sampling clock phase in
11.25° increments. Default value is decimal 16.
PHASE_4–0 X X X
PLL Control.
Configuration Register No. 2.
Clamp Control Register.
Reserved.
Default (hex)
80
24
00
00
00
Register Definitions
PLL Control Register (01)
Bit no.
1-0
2
3
7-4
Name
SUBDIV_1-0
PLLFAZ
–
PLLN_3-0
Type
R/W
R/W
R/W
R/W
Description
PLL Subdivide ratio. Selects the ratio of the divider following the PLL.
00: divide-by 1
01: divide-by 2
10: divide-by 4
11: reserved
X X X X X X SUBDIV_1–0
PLL Sub-divider Phase. Selects the phase of the divide-by-2 output.
(Invalid for other outputs)
Reserved.
PLL divide ratio, LSBs. PLLN + 1 = total number of pixels per horizontal line.
PLLN_3–0 X X X X
Configuration Register 1 (0A)
Bit no.
0
1
2
3
4
5
6
7
Name
XCKSEL
XCLAMPOL
XCLAMP
COASTPOL
HSPOL
—
—
Type
R/W
R/W
R/W
R/W
R/W
R
R
Description
External Clock Select. Select internal clock source.
0: Internal PLL
1: XCK input.
External Clamp Polarity. Select clamp polarity.
0: Active L.
1: Active H.
External Clamp Select. Select clamp source.
0: Internally generated by PLL referenced to HSIN.
1: External CLAMP input.
Coast Polarity. Select COAST input polarity.
0: Active L.
1: Active H.
HSIN Polarity. Select horizontal sync input polarity. PLL is locked to selected
edge:
0: Falling edge.
1: Rising edge.
1:
1:
6
REV. 1.2.15 1/14/02