FMS9875 Datasheet, PDF (4/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

PRODUCT SPECIFICATION
FMS9875
Pin Descriptions
Pin Name
Pin No.
Converter Channels
YG_IN, BP_IN, RP_IN 3, 9, 15
YG_REF, BP_REF, 4, 10, 16
RP_REF
DYG_7-0
76–83
DPB_7-0
63–70
DPR_7-0
51–58
Timing Generator
CLAMP
21
INVSCK
20
XCK
34
DCK
86
DCK
87
HSOUT
88
Phase Locked Loop
HSIN
30
COAST
31
Type/Value
Input
Input
Output
Output
Output
Input
Input
Input
Output
Output
Output
Schmitt
Input
Pin Function Description
Analog Inputs. RGB or YP_BP_R.
Clamp Reference Inputs. Voltage reference inputs for YG, BP and
RP clamps.
Luminance/Green Channel Data Output.
P_B/Blue Channel Data Output.
P_R/Red Channel Data Output.
External Clamp Input.
Invert Sampling Clock. Inverts SCK, the internal clock sampling the
analog inputs. Supports Alternate Pixel Sampling mode for capture
pixel rates up to 216Ms/s.
External Clock input. Enabled if register bit, XCKSEL = H.
Replaces PXCK clock generated by PLL. If unused, connect to
ground through a 10kΩ resistor.
Output Data Clock. Clock for strobing output data to external logic.
Output Data Clock Inverted. Inverted clock for strobing output data
to external logic.
Horizontal Sync Output. Reconstructed HSYNC delayed by
FMS9875 latency with leading edge synchronized to start of data
output. Polarity is always active HIGH.
Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V
source should be clamped at 3.3V or current limited, to prevent
overdriving ESD protection diodes.
PLL COAST. Extraneous or missing horizontal sync pulses can be
ignored by asserting the COAST input. With COAST asserted, the
HSIN signal is ignored by the PLL without affecting PXCK and the
derived clocks: SCK, DCK and DCK. With register bit, COASTPOL = 1:
COAST = L: PLL locked to HSIN.
COAST = H: PLL VCO input floats with HSIN disregarded
LPF
Sync Stripper
ACS_IN
DCS_OUT
Control
SDA
SCL
A₀
A₁
PWRDN
COAST polarity may be inverted using the COASTPOL register bit.
35
Passive PLL Low Pass Filter. Connect recommended PLL filter to LPF pin.
(see Schematic, PLL Filter)
2
Analog Composite Sync Input. Input to sync stripper with 150mV
threshold.
89
Digital Composite Sync Output. Output from sync stripper.
22 Bi-directional Serial Port Data. Bi-directional data (I²C/SMBUS).
23
Input
Serial Port Clock. Clock input (I²C/SMBUS).
24
Input Address bit 0. Lower bit of serial port address.
25
Input Address bit 1. Upper bit of serial port address.
96
Input Power Down/Output Control. Powers down the FMS9875 with
outputs high impedance.
4
REV. 1.2.15 1/14/02