FMS9875 Datasheet, PDF (17/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

FMS9875
PRODUCT SPECIFICATION
Values of IPUMP and FVCO are set through the PLL
Configuration Register (0x0C). Recommended external filter
components are shown in Figure 16. RF quality ±10%
ceramic capacitors with X7R dielectric are recommended.
C1
0.18µF
R1
1.5K
VDDP
C2
0.018µF
LPF
Figure 16. Schematic, PLL Filter.
Loop performance is established by setting:
1. VCO frequency range through FVCO_1-0. (see Table 8)
2. Charge Pump Current through IPUMP_2-0. (see Table 9)
3. External loop filter component values.
Table 8. VCO Frequency Bands
FVCO_2-0 Frequency Range (MHz) KVCO (MHz/V)
00
10–40
35
01
10–70
60
10
20–120
80
11
20–150
95
1. Use 2X over-sampling. For example with NTSC-601,
the 1X sample rate should be 13.5 MHz. If the divide
ratio is increased from 858 (PLLN = 857) to 1716
(PLLN = 1715), the sampling rate is 27 MHz.
2. Use 1X sampling by doubling the VCO frequency, then
dividing the PLL frequency by two. For example, with
NTSC-601, the divide ratio is doubled to 1716
(PLLN = 1715), then the sub-divide ratio is set to two
(SUBDIV_1-0 = 01) to reduce the sampling rate from
27 MHz to 13.5 MHz with 858 pixels per line.
COAST
When COAST is active, PLL lock to HSIN is disabled, while
the VCO frequency is retained. VCO frequency remains
stable over several lines without updates from HSIN.
COAST can be connected directly to the vertical sync signal
or supplied by the graphics controller. If 1/2H pulses are
present within HSIN, the COAST period must encompass all
1/2H pulses. COAST polarity may be inverted using the
COASTPOL register bit. In the description below, the setting
COASTPOL = H is used.
Operation of COAST is depicted in Figure 17. HSOUT
polarity is always positive. When COAST = L, HSOUT
tracks HSIN (shown with postive polarity in Figure 1):
1. HSOUT rising edge tracks HSIN delayed by a few pixels.
2. HSOUT falling edge tracks the trailing edge of HSIN
with no delay.
Table 9. Charge Pump Current Levels
IPUMP_2-0
000
001
010
011
100
101
110
111
Current (µA)
50
100
150
250
350
500
750
1500
Setting PHASE_4-0 selects the sampling phase of SCK rela-
tive to PXCK in 32 steps of 11.25°. Phase of the output data,
DCK and DCK is slaved to the SCK phase.
RMS Clock jitter is less than 2% of pixel period in all operat-
ing modes.
When COAST = H, the PLL flywheels, disregarding the
incoming HSIN references, while the HSOUT waveform
depends upon the state of HSIN.
1. If HSIN = H:
a.) HSOUT rising edge remains locked to the PLL.
b.) HSOUT trailing edge falls after 50% of the HSOUT
period has expired.
2. HSIN transitions:
a.) HSOUT rising edge remains locked to the PLL.
b.) HSOUT falling edge is terminated by the trailing
edge of HSIN.
3. If HSIN = L, then HSOUT = L
At frequencies below 80 MHz, the percentage jitter begins to
rise. Increased jitter at low frequencies can be counteracted
in either of two ways:
REV. 1.2.15 1/14/02
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