FMS9875 Datasheet, PDF (7/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

FMS9875
PRODUCT SPECIFICATION
PLL Configuration Register (0C)
Bit no.
Name
Type Description
1-0
—
4-2
IPUMP_2-0 R/W Charge Pump Current. Selects Charge Pump current (µA).
000: 50
001: 100
010: 150
011: 250
100: 350
101: 500
110: 750
111: 1500
6-5
FVCO_1-0 R/W VCO Frequency Range. Selects VCO frequency range (MHz).
00: 10–40
01: 10–70
10: 20–120
11: 20–150
7
—
R/W Reserved.
0: Run.
1: (reserved).
Configuration Register 2 (0D)
Bit no.
0
Name
—
Type Description
— Reserved. Set to 0.
3-1
REV
R Revision Number. Die revision number.
4 OUTPHASE R/W Output Data Phase. In the alternate pixel mode, selects either odd (1, 3, 5, …)
or even (2, 4, 6 ….) samples following the HSYNC leading edge to be emitted
from output data ports.
0: Even samples
1: Odd samples
5
TWOS
R/W P_BP_R Data Output Format.
0: Offset binary.
1: Two’s complement.
6
PRFIRST R/W P_BP_R Data Output Timing.
0: P_B data first, P_R data second.
1: P_R data first, P_B data second.
7
422
R/W Output Data Format.
0: 444
1: 422 with P_BP_R multiplexed onto the DBP_7-0 output.
REV. 1.2.15 1/14/02
7