FMS9875 Datasheet, PDF (2/29 Pages) Fairchild Semiconductor – Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

PRODUCT SPECIFICATION
Architectural Overview
Three separate digitizer channels are controlled by common
timing signals derived from the Timing Generator. A/D clock
signals can be derived from either a PLL or an external clock
XCK. With the PLL selected, A/D clocks track the incoming
horizontal sync signal connected to the HSIN input. Setup is
controlled by registers that are accessible through the serial
interface.
Conversion Channels
Typical RGB or YP_BP_R input signals, GYIN, BPIN, and
RPIN are ground referenced with 700mV amplitude. If a
sync signal is embedded then the usual format is sync on
green or Y with the sync tip at ground, the black level
elevated to 300mV and peak green at 1000mV. Either type
of input can be accepted by using the clamp function with
AC coupling.
Clamps
AC coupled input video signals must be level shifted to
match the signal and A/D converter reference levels during
the back porch (see Figure 1). Y/G inputs should be clamped
to the A/D converter lower reference level. P_BP_R signals
should be clamped to the A/D converter midrange level
(nominally 350 mV), which is 50% of full scale (nominally
700 mV).
P_BIN, P_RIN
+350 mV
-350 mV
+700 mV
YG_IN
ICLAMP
Figure 1. Clamping to the back-porch
Clamp pulses, ICLAMP, are derived from internal Timing
and Control logic or from the external CLAMP input. Clamp
timing is common to the three input channels.
With the A/D range set to 700mV ground referenced, clamp
levels are:
• RGB: 000mV
• Y: 000mV
• P_BP_R: +350mV
Clamp levels can be set through the registers or through the
YG_REF, BP_REF and RP_REF pins.
Gain and Offset
Gain and Offset registers serve two functions: 1) Adjustment
of contrast and brightness by setting RGB values in tandems.
2) Matching the gain and offsets between channels, by
setting RGB values individually to obtain the same output
levels at zero and full-scale.
2
FMS9875
A/D conversion range can be matched to the amplitude of the
incoming video signal by programming Gain Registers
GGY, GBP and GRP, which vary sensitivity (LSB/volt) over
a 2:1 range. Incoming video signal amplitudes varying from
0.5 to 1.0 volt can be accommodated.
Input offset voltage of each converter is programmable in 1
LSB steps through the 6-bit OSGY, OSBP and OSRP regis-
ters. Range of adjustment is equivalent to –31 to +32 LSB.
A/D Converter
Each A/D converter digitizes the analog input into 8-bit data
words. Latency is 5–5¹/2 clock cycles, depending upon the
state of the INVSCK pin.
V_REFIN is the source of reference voltage for the three A/D
converters. V_REFIN can be connected to either the internal
bandgap voltage, V_REFOUT or an external voltage.
Output Data Configuration
For RGB outputs, data format is unsigned binary: 00
corresponds to the lowest input; FF corresponds to the
highest input.
For YP_BP_R outputs, the data format is:
• Y (0 to 700mV input): unsigned binary.
• P_BP_R (±350mV input): twos-complement or offset binary.
Output data format is:
• 24-bit YP_BP_R444
• 16-bit YP_BP_R422
With 422 sampling, P_BP_R samples are coincident with even
samples of Y, beginning with 0.
HSOUT, L-to-H transition identifies the first sample.
Timing and Control
Timing and Control logic encompasses the Timing Generator,
PLL and Serial Interface.
Timing Generator
All internal clock and synchronization signals are generated
by the Timing Generator. Master Clock source is either the
PLL or the external clock input, XCK. Register bit, XCKSEL
selects the Master Clock source. Two clocks are generated.
Sampling clock, SCK is supplied to all three A/D converters.
Phase of SCK (relative to HSIN) can be adjusted in 32 11.25
degree phase increments using the 5-bit PHASE register.
Output data clocks, DCK and DCK are provided for
synchronizing data transfer from the digitizer outputs.
DCK and DCK are slaved to SCK.
Incoming horizontal sync HS_IN is propagated by the Timing
and Control to HS_OUT with a delay that aligns the leading
edge with the output data.
REV. 1.2.15 1/14/02