XR16C872 Datasheet, PDF (5/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

DISCONTINUED
XR16C872
PIN DESCRIPTION
Signal Type Definition. The following signal type definitions are from the 872 device point of view.
I
Standard input
O
Standard active output
OT24
Tri-state output
IOP14 Tri-state bi-directional input/output
IO24
Tri-state bi-directional input/output
Name
Pin # Type
HOST INTERFACE
A0-A15
2-15
I
17,18
Pin Description
ISA Bus Address. All 16 bits are used during PnP auto configuration
sequence with external EEPROM providing the resource data. In the
manual configuration mode A0-A10 are used for decoding COM1-4 and
LPT1-2 addresses. After auto or manual configuration, bits A0-A2 select
UART internal registers and A3-A10 are used to select UART A or B, or
the 1284 printer port.
D0-D7
30-21
IO24
ISA Data Bus. These are the eight three state data lines for transferring
data to or from the controlling CPU. D0 is the least significant bit and the
first data bit in a transmit or receive serial data stream.
AEN
19
I Address Enable. Active high to validate A0-A15 address lines during Direct
Memory Access operation on the ISA bus. Connect to logic 0 when it is not used.
IOR#
99
I Read Strobe. A logic 0 transition on this pin will request the contents of
an Internal register defined by address bits A0-A2 for either UART channels
A/B or A0-A1 for the printer port, be place onto D0-D7 data bus for a read
cycle by the CPU.
IOW#
100
I Write Strobe. A logic 1 transition on this pin will transfer the data on the
data bus (D0-D7), as defined by either address bits A0-A2 for UART channels
A/B or A0-A1 for the printer port, into an internal register during a write cycle
from the CPU.
IRQ15
IRQ12-10
IRQ9
IRQ3-7
86
87-89
97
92-96
OT24 Interrupt Request Lines. These are three state active high interrupt lines to
controlling CPU when an interrupt request is generated by the UART
channel A/B or 1284 printer port.
DREQ5
DREQ3
DREQ1
DREQ0
78
OT24 DMA Request Channel 0,1,3 and 5. These are three state active high
79
outputs with internal weak pull down resistor. DMA request is used
80
by the 1284 parallel port during ECP and FIFO mode.
81
DACK5#
DACK3#
DACK1#
DACK0#
82
I DMA Acknowledge Channel 0,1,3 and 5. These are active low inputs
83
and are used by the 1284 parallel port during ECP and FIFO mode.
84
85
Rev. 1.00
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