XR16C872 Datasheet, PDF (23/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

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XR16C872
Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1; resetting IER bits 0-
3 enables the 850 in the FIFO polled mode of operation.
Since the receiver and transmitter have separate bits in
the LSR either or both can be used in the polled mode
by selecting respective transmit or receive control bit(s).
A) LSR BIT-0 will be a logic 1 as long as there is one byte
in the receive FIFO.
B) LSR BIT 1-4 will indicate if an overrun error occurred
in the receiver.
C) LSR BIT-5 will indicate when the transmit FIFO is
empty.
D) LSR BIT-6 will indicate when both the transmit FIFO
and transmit shift register are empty.
E) LSR BIT-7 will indicate any data errors within the
receive FIFO. This bit will clear when the error byte is
unloaded.
IER BIT-0:
Logic 0 = Disable the receiver ready interrupt. (normal
default condition)
Logic 1 = Enable the receiver ready interrupt. The
receiver ready interrupt is cleared when LSR is read.
IER BIT-1:
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
Logic 1 = Enable the transmitter empty interrupt. The
transmitter empty interrupt is cleared when ISR is read.
IER BIT-2:
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt. The
receiver line interrupt is cleared when LSR is read.
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
The modem status interrupt is cleared when MSR is
read.
IER BIT -4:
Logic 0 = Disable sleep mode. (normal default condi-
tion)
Logic 1 = Enable sleep mode. See Sleep Mode section
for details.
IER BIT-5:
Logic 0 = Disable the software flow control, receive
Xoff-det interrupt. (normal default condition)
Logic 1 = Enable the software flow control, receive
Xoff-det interrupt. The Xoff-det interrupt is cleared by
reading the ISR register or upon receiving a Xon charac-
ter. Also, when Special Character mode is enabled
(EFR-bit 5 =1) reading the ISR register or a following
received character will clear the interrupt.
IER BIT-6:
Logic 0 = Disable the RTS interrupt. (normal default
condition)
Logic 1 = Enable the RTS interrupt. The UART issues
an interrupt when the RTS# pin transitions from a logic
0 to a logic 1 as reported in MSR bit-register. The
interrupt is cleared by reading the MSR register.
IER BIT-7:
Logic 0 = Disable the CTS interrupt. (normal default
condition)
Logic 1 = Enable the CTS interrupt. The UART issues
an interrupt when CTS# pin transitions from a logic 0 to
a logic 1 as reported in MSR register. The interrupt is
cleared by reading the MSR register.
FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the
FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are
defined as follows:
DMA MODE
Mode 0 Set and enable the interrupt for each single
character transmit or receive operation. Transmit empty
interrupt will be generated whenever the Transmit Hold-
ing Register (THR) is empty and receive ready interrupt
will be generated whenever the Receive Holding Regis-
ter (RHR) is loaded with a character. However, the RX
FIFO continues to receive data up to its limit.
Rev. 1.00
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