XR16C872 Datasheet, PDF (37/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

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XR16C872
Cnfg-B Bit 3-5:
In the PnP mode IRQ assignment is made through auto
configuration. Manual mode defaults to IRQ 7.
IOW# IOR# IRQ
000 001 7
001 001 7 (default)
010 010 7
011 001 7
100 001 7
101 001 7
110 001 7
111 111 7
Cnfg-B Bit-6:
Returns the true value of the selected IRQ pad.
Cnfg-B Bit-7:
Indicates RLE compression is not supported.
ECR Bit-3 = DMA
DCR Bit-5 = DIRection
DMA DIR CONDITION
0
0
8 empty bytes in the FIFO.
0
1
8 filled bytes in the FIFO.
1
X DMA Terminal Count (TC).
ECR BIT-3:
This bit disables DMA when set low. When set high, a
low on ServiceIntr will enable DMA requests.
0 = DMA disabled, DRQx pin is three-stated.
1 = DMA enabled
ECR Bit-4:
When low, this bit (ErrIntrEn#) enables a pulsed inter-
rupt if ERR# (Fault#) is low. The interrupt is only enabled
in ECP mode.
EXTENDED CONTROL REGISTER ( ECR )
The Extended Control Register has a system RESET
state of 10010101. The significance of the bits is defined
by the ECP specification as:
ECR Bit 5-7:
This field can be set to any value if the current value is
000 or 001. If the current value is not 000 or 001, then
the field can only be written to 000 or 001. The modes
are defined as:
ECR Bit-0:
This read-only bit returns FIFO empty status (FIFO-E)
and is forced high unless PPF, ECP, or TST mode is
selected.
0 = At least one byte of data contains in the FIFO.
1 = FIFO is empty.
ECR Bit-1:
This read-only bit returns FIFO full status (FIFO-F) and
is forced low unless PPF, ECP, or TST mode is
selected.
0 = At least one empty location is available in the FIFO.
1 = FIFO is full.
ECR Bit-2:
When low, this bit (ServiceIntr) enables a pulsed inter-
rupt and enables DMA requests (if bit-3 is set). If the
enabled interrupt occurs, this bit is automatically re-
turned to a high. The interrupt conditions are:
MODE NAME DESCRIPTION
000
SPP
Standard, output only. DCR
Bit-5 is forced to “0”.
001
PS2
Bi-directional PS/2 parallel
port. FIFO is disabled
010
PPF
FIFOed, output only. DCR Bit-
5 is forced to “0”.
011
ECP
ECP FIFOed port with RLE de-
compression. FIFO direction
is controlled by DCR Bit-5.
100
EPP
EPP mode.
101
-
reserved
110
TST
FIFO test mode. FIFO is ac-
cessible via TFIFO register.
111
CFG
Configuration A/B register en-
able.
Rev. 1.00
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