XR16C872 Datasheet, PDF (38/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

XR16C872
DISCONTINUED
OPERATION
SPP MODE
This is ECR mode 000 (system RESET mode).
In this output-only mode the host data is registered to PD[7:0] at the trailing edge of IOW#; PDIR is driven low;
STROBE#, AUTOFD#, INIT#, and SELCTIN# are open-drain; and all timing is managed by the host through DSR
and DCR registers.
PS2 MODE
This is ECR mode 001.
In this bi-directional mode the host output data is registered to PD[7:0] at the trailing edge of IOW#, PDIR is driven
by DIR to allow peripheral data input, AUTOFD#, INIT#, and SELCTIN# are totem-pole, and all timing is managed
by the host through DSR and DCR registers.
PPF MODE
This is ECR mode 010.
In this output-only mode the host data is written to the FIFO with I/O writes to address 400 or by DMA writes; PDIR
is driven low. FIFO data is automatically registered to PD[7:0] whenever the FIFO-E bit is low (data available), and
timing is generated by controller logic that handshakes STROBE# (controller) with BUSY (peripheral).
ECP MODE
This is ECR mode 011.
In this bi-directional mode the host data is written to the FIFO with I/O writes to address 000, 400 or DMA; PDIR is
driven by DIR (can only be set in ECR mode 001); AUTOFD#, INIT, and SELCTIN# are totem-pole. I/O writes to
address 000 will write a low into the FIFO tag bit, while I/O writes to address 400 or DMA will insert a high.
ECP FORWARD MODE (PDIR = 0)
FIFO data is automatically registered to PD[7:0] whenever the FIFO-E bit is low (data available), and timing is
generated by controller logic that handshakes STROBE# (controller) with BUSY (peripheral). Data from the FIFO
tag bit is output on AUTOFD# after being registered simultaneous with FIFO data.
ECP REVERSE MODE (PDIR = 1)
PD[7:0] data and BUSY are latched into the FIFO and tag bit respectively at the trailing edge of AUTOFD# if FIFO-
F = 0. Timing is generated by controller logic that handshakes ACK# (peripheral) with AUTOFD# (controller).
EPP MODE
This is ECR mode 100.
In this bi-directional mode, I/O writes will latch host output data at the trailing edge of IOW#, and peripheral input
data will be latched at the trailing edge of SELCTIN# or AUTOFD#. PDIR, and STROBE# are driven by the state of
IOW# (DCR bits 5 and 0 must be set low).
EPP mode allows buffered access between the PC bus and the peripheral with timing provided by the peripheral
via BUSY handshake into IOCHRDY. I/O cycles with address 003 - 007 will immediately drive IOCHRDY low.
STROBE# will go low and PD[7:0] is allowed to change (write cycles) after BUSY has been low for at least 60n second.
(this delay may have elapsed prior to cycle initiation), immediately followed by a low driven on SELCTIN# for address
003 or AUTOLF# (DATASTB*) for address 004 - 007 (read and write cycles). When BUSY returns high for a minimum
of 60n second, IOCHRDY and the active strobe will be driven high - allowing the host to complete the I/O transaction.
Rev. 1.00
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