XR16C872 Datasheet, PDF (22/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

XR16C872
DISCONTINUED
The UARTs have Device Identification and Device
Revision code to distinguish the part with others. It is
suggested to the user to read the identification and
revision information from the part only during the power
on initialization routine to avoid disturbing the baud rate
generator during normal operation.
To read the identification number from the device, it is
required to set the baud rate generator divisor latch to
logc 1 (LCR bit-7 = logic 1) and set the content of the
baud rate generator DLL and DLM registers to 0x00.
Then read the content of DLM=0x10 for XR16C850 type
and the content of DLL for the device revision with 0x01
represents revision-A and 0x02 for revision-B, and so
forth.
At the beginning of UART Initiation routine:
Write LCR bit-7=1
Write DLM = 0x00
Write DLL = 0x00
Read DLM for the UART type number (0x10)
Read DLL for the UART revision number (0x02)
Transmit and Receive Data Register
The serial transmitter section consists of a 8-bit Transmit
Hold Register (THR) which is part of the transmit FIFO
and Transmit Shift Register (TSR). The status of the THR
and TSR are provided in the Line Status Register (LSR).
Writing to THR address location transfers the contents
of the data bus (D7-D0) to the THR, providing that the
THR or TSR flag is set. The THR empty flag is set to logic
1 when the transmit FIFO has room for more data. The
flag indicates either that the transmit holding register
becomes empty in the non-FIFO mode or at the preset
transmit trigger level when the transmit FIFO is enabled.
The TSR flag always indicates the transmitter is empty
and it has nothing to shift out. This flag can be use for
directional control in half duplex operations.
The serial receive section also contains a 11-bit Receive
Holding Register (RHR) which is part of the receive
FIFO. Receive data is unloaded by reading the RHR
register address location. The receive section provides
a mechanism to detects false starts. On the falling edge
of a start or false start bit on RX input, an internal
sampling counter starts counting clocks at 16x of the
operating data rate. After 7 1/2 clocks the incoming start
bit time should be at the center of the bit time. At this time
the start bit is sampled and if it is still a logic 0 it is
validated. If false, the detection sequence starts all over
again. Evaluating the start bit in this manner and
validating data bits and stop bit also in the middle of the
bit time helps to ensure the integrity of the receiving
character. Receive errors such as Framing, Parity, and
Overrun are saved in the receive FIFO and posted in
the LSR upon each data byte becomes available to the
CPU. The receive FIFO is actually a 11-bit wide FIFO
including the 3 receive error bits. The receiver FIFO
pointer is bumped upon a data byte read operation.
Therefore, it is necessary for the user to read the error
bits prior reading the data byte.
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts for receiver ready, transmitter empty, line status,
and modem status. It also optionally includes CTS#,
RTS# and Xoff interrupts when enabled by EFR register
bit-4. These interrupts are wired Or’ed to the INT output
pin. See IER register description for more detail.
Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR bit-0 = logic 1) and receive
interrupt (IER bit-0 = logic 1) are enabled, the receive
interrupt and register status will reflect the following:
A) The receive data interrupt is issued when the receive
FIFO has reached the programmed trigger level. The
interrupt clears when 1) upon reading LSR register or
2) FIFO content drops below the programmed trigger
level.
B) Receive FIFO status is also reflected in the ISR
register when the FIFO trigger level has reached the
programmed level. The ISR register status bit will clear
only when the FIFO content drops below the pro-
grammed trigger level.
C) The receive data ready bit (LSR bit-0) is set as soon
as a character is transferred from the receive shift
register to the receive FIFO. This bit is reset when the
FIFO becomes empty.
Rev. 1.00
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