XR16C872 Datasheet, PDF (35/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

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XR16C872
STANDARD DEFINITIONS
• Forward direction only.
Compatible Mode, “Centronics” or standard mode
(SPP).
• Reverse direction only.
Nibble mode:
4 bits at a time using status lines for data “Hewlett
Packard Bi-tronics”.
msecond TimeOut elapsed during the last EPP read or
write cycle (this TimeOut also aborts the EPP cycle).
This status bit is cleared by exiting EPP mode or by the
host writing a high to bit-0 of this register.
DSR Bit 1-2:
Reserved, logic one.
DSR Bit-3:
The true state of the ERR# pin.
• Bi-directional.
EPP:
Enhanced Parallel Port, used primarily by non-
printer peripherals.
DSR Bit-4:
The true state of the SELECT pin.
DSR Bit-5:
The true state of the PE pin.
ECP:
Extended Capability Port, used primarily by latest
generation of printers, scanners and external stor
age and CD drives for higher data transfer rate.
DATA REGISTER (DATA )
DATA Bit 0-7:
For host output cycles in SPP mode (ECR mode 000)
or PS/2 mode (ECR mode 001), data from the host is
registered at the trailing edge of IOW#. On host input
cycles, data at the peripheral port is passed through to
the host data bus.
ECP FIFO ADDRESS ( ECP-AFIFO )
DSR Bit-6:
The true state of the ACK# pin.
DSR Bit-7:
The complement of the BUSY pad.
DATA CONTROL REGISTER ( DCR )
DCR Bit-0:
The complement of this bit drives STROBE#, and the
complement of the pad state is returned for read.
DCR Bit-1:
The complement of this bit drives AUTOFD#, and the
complement of the pad state is returned for read.
ECP-AFIFO Bit 0-7:
This port is only available for programmed I/O (non-
DMA), and only has significance for host write. Data
written to this port is stored in the FIFO if FIFO-F = 0 and
will be lost if FIFO-F = 1. A 9th FIFO bit (tag) is set low
on write. A read from this port is the same as a read at
400.
DCR Bit-2:
This bit drives INIT#, and the pad state is returned for
read.
DCR Bit-3:
The complement of this bit drives SELCTIN#, and the
complement of the pad state is returned for read.
DATA STATUS REGISTER ( DSR )
This status register is read-only except for bit-0, and all
bits are latched for the duration of IOR#.
DSR Bit-0:
If EPP mode is not selected, this bit returns logic one.
During EPP mode, bit-0 will return a high if the EPP 10
DCR Bit-4:
Ack Interrupt Enable set to a high will generate an
interrupt when ACK# is low. When either returns to a
high state, this interrupt source will go in-active. This
interrupt is not pulsed.
DCR Bit-5:
Peripheral port direction, OUT = 0 and IN = 1.
Rev. 1.00
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