XR16C872 Datasheet, PDF (27/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

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XR16C872
LCR BIT 0-1: (logic 0 or cleared is the default condition)
These two bits specify the word length to be transmitted
or received. The upper unused bit(s) in the received
data byte is set to zero.
BIT-1 BIT-0
Word length
LCR BIT-5 = logic 0, parity is not forced (normal default
condition)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive data.
0
0
5
0
1
6
1
0
7
1
1
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in conjunc-
tion with the programmed word length.
LCR LCR LCR
Bit-3 Bit-4 Bit-5
0
X
X
1
0
0
1
1
0
1
0
1
1
1
1
Parity Selection
No parity
Odd parity
Even parity
Force parity=“1”
Forced parity= 0”
BIT-2
0
1
1
Word
length
5,6,7,8
5
6,7,8
Stop bit
length
(Bit time(s))
1
1-1/2
2
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, the receiver checks and reports parity error in the
LSR register. The parity is not presented in the received
data byte.
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The receiver
must be programmed to check the same format. (normal
default condition)
Logic 1 = EVEN Parity is generated by forcing an even
the number of logic 1’s in the transmitted. The receiver
must be programmed to check the same format.
LCR BIT-6:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to a
logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
LCR BIT-7:
The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled. (normal default condi-
tion)
Logic 1 = Select baud rate divisors (DLL and DLM) and
enhanced feature register set enabled
Modem Control Register (MCR)
This register controls the interface with the modem or a
peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal default
condition)
Logic 1 = Force -DTR output to a logic 0.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the forced
parity format.
MCR BIT-1:
Logic 0 = Force RTS# output to a logic 1. (normal default
condition)
Rev. 1.00
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