XR16C872 Datasheet, PDF (44/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

XR16C872
DISCONTINUED
“ECP MODE” SIGNAL DESCRIPTIONS
Signal
Name
Signal
Type
ECP mode
Name
Description
STROBE#
O
HostClk
Used with PeriphAck to transfer data or address information in
the forward direction.
AUTOFD#
O
HostAck
Provides Command / Data status in the forward direction. Used
with PeriphClk to transfer data in the reverse direction.
SELCTIN#
O
1284Active
Set high when host is in a 1284 transfer mode.
INIT#
O
ReverseReq# Driven low to put the channel in reverse direction.
ACK#
I
PeriphClk
Used with HostAck to transfer data in the reverse direction.
BUSY
I
PeriphAck
Used with HostClk to transfer data or address information in the
forward direction. Provides Command / Data status in the reverse
direction.
PE
I
AckReverse# Driven low to acknowledge ReverseRequest.
SELECT
I
Xflag
Extensibility flag.
ERR#
I
PeriphReq# Set low by peripheral to indicate that reverse dat is available.
PD0-PD7
I/O
D0-D7
Bi-directional data lines.
ECP Mode Forward Data and Command Transfer Cycle
1. Host places data on the data lines and indicates a data cycle by setting HostAck high.
2. Host asserts HostClk low to indicate valid data.
3. Peripheral acknowledge host by setting PeriphAck high.
4. Host sets HostClk high. This is the edge that should be used to clock the data in to the peripheral.
5. Peripheral sets PeriphAck low to indicate that it is ready for the next byte.
6. The cycle repeats, but this time it is command cycle because HostAck is low.
ECP Mode Reverse Data and Command Transfer Cycle
1. The Host requests a reverse channel transfer by setting ReverseReq# low.
2. The peripheral signals that it is okay to proceed by setting AckReverse# low.
3. The peripheral places data on the data lines and indicates a data cycle by setting PeriphAck high.
4. Peripheral asserts PeriphClk low to indicate valid data.
5. Host acknowledges by setting HostAck high.
6. Peripheral sets PeriphClk high. This is the edge that should be used to clock the data in to the host.
7. Host sets HostAck low to indicate that it is ready for the next byte.
8. The cycle repeats, but this time it is a Command cycle because PeriphAck is low.
Rev. 1.00
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